Subject: [sv-ec] FW: BOUNCE sv-ec@eda.org: Non-member submission from ["Bassam Tabbara"
From Bassam
David W. Smith
Synopsys, Inc.
Voice: 503.547.6467
-----Original Message-----
>From owner-sv-ec Fri Dec 6 17:00:24 2002
Kev., the last thing in one cycle is not the same as the first thing in
My point is this should be clearly defined ... so that both -your-
My point clear now ?
Salam
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: Fri Dec 06 2002 - 17:25:34 PST
From: David W. Smith (david.smith@synopsys.com)
Date: Fri Dec 06 2002 - 17:25:38 PST
Synopsys Scientist
Synopsys Technology Park
2025 NW Cornelius Pass Road
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Email: david.smith@synopsys.com
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Subject: BOUNCE sv-ec@eda.org: Non-member submission from ["Bassam
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From: "Bassam Tabbara" <bassam@novas.com>
To: "Kevin Cameron x3251" <Kevin.Cameron@nsc.com>,
<sv-ec@server.eda.org>
Cc: <sv-ac@server.eda.org>, "Dr. Bassam Tabbara" <bassam@novas.com>
Subject: RE: [sv-ac] Verification phase
Date: Fri, 6 Dec 2002 17:00:20 -0800
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FILETIME=[04132120:01C29D8C]
the next cycle, by virtue of that pesky "next" word there. -My- opinion
is that $monitor and assert should be in same spot. As you know, the
issue of rosynch callback, rwsynch callback, nonblocking,
$monitor/$strobe has been interpreted, re-interpreted, and
mis-interpreted for ages, and that is when only "design" is there, with
"stimulus" this is bound to be even more vague.
opinion and mine can at least be resolved by clearly defined semantics
in the LRM, if not made allowance for i.e. one could argue that this is
a degree of freedom that must be left to tool providers, in which case
that statement should be made. Therefore re-emphasizing the need for
splitting the two stages, assertion and stimulus.
-Bassam.