Subject: [sv-ec] RE: [sv-ac] Verification phase
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Fri Dec 06 2002 - 17:31:01 PST
> From Bassam@novas.com Fri Dec 6 16:58:21 2002
>
> Kev., the last thing in one cycle is not the same as the first thing in the
> next cycle, by virtue of that pesky "next" word there. -My- opinion is that
> $monitor and assert should be in same spot. As you know, the issue of
> rosynch callback, rwsynch callback, nonblocking, $monitor/$strobe has been
> interpreted, re-interpreted, and mis-interpreted for ages, and that is when
> only "design" is there, with "stimulus" this is bound to be even more vague.
If nothing has happened in the design between the end of one cycle at the
start of the next then they are virtually the same.
> My point is this should be clearly defined ... so that both -your- opinion
> and mine can at least be resolved by clearly defined semantics in the LRM,
> if not made allowance for i.e. one could argue that this is a degree of
> freedom that must be left to tool providers, in which case that statement
> should be made. Therefore re-emphasizing the need for splitting the two
> stages, assertion and stimulus.
>
> My point clear now ?
I thought I was clearly splitting them :-)
Kev.
> Salam
> -Bassam.
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