Subject: Re: [sv-ec] Re: $wait_all/any/...
From: Stuart Sutherland (stuart@sutherland-hdl.com)
Date: Fri Dec 20 2002 - 16:58:02 PST
Hmmm, maybe you are on to something, Kevin. Perhaps we could use "wait
alles", "wait einige" und "wait keine". While we are at it, we could
deprecate "and", and replace it with "und". We may run into a problem with
replacing "or", however. The German word "oder" is also an English word,
with an entirely different meaning.
I'm just kidding of course! ;)
Seriously, as a Verilog user, ultimately all I want is new OR simplified
functionality, in an intuitive form. As one who often teaches engineers
who have never seen Verilog how to use the language without shooting
themselves in the foot, simplicity and intuitiveness are critical
characteristics of whatever enhancements are made.
Stu
At 04:27 PM 12/20/2002, Kevin Cameron x3251 wrote:
> > From: "Stuart Sutherland" <stuart@sutherland-hdl.com>
> >
> > Please see my comments inserted after Kevin's, below...
> >
> > Stu
>...
> >
> > I absolutely cannot accept using numbers to modify the behavior. "join 0"
> > and such would create unreadable code, unless the user was kind enough to
> > add some comments. Any of the alternate methods that have been tossed
> > around are far, far better than making the code excessively
> > obfuscated. That's just my opinion, of course.
>
>BTW, "all","any" and "none" are all English words, which of course have no
>meaning to non-english speakers. 0,1 have the same meaning across most of
>the world.
>
>
>Froehliche Weihnachten und ein glu"ckliches Neues Jahr!
>
>Kev.
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Stuart Sutherland Sutherland HDL Inc.
stuart@sutherland-hdl.com 22805 SW 92nd Place
phone: 503-692-0898 Tualatin, OR 97062
www.sutherland-hdl.com
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