Subject: [sv-ec] Agenda for 6 January 2003 Meeting
From: David W. Smith (david.smith@synopsys.com)
Date: Mon Jan 06 2003 - 09:32:49 PST
There will be the normal meeting for the SV-EC committee from 11:00am until
1:00pm PDT on Monday 6 January 2003.
Dial in Information
* PARTICIPANT CODE: 516134
* Toll Free Dial In Number: (877)233-7845
* International Access/Caller Paid Dial In Number: (505)766-5458
Agenda
1, Review minutes from the 16 December meeting and approve
2. Review Action items (see minutes from 16 December meeting)
3. Update on meeting schedule
a. go to weekly meetings
b. Full day meeting on January 21.
4. Review LRM
a. Review and approve CH-21 on section 3.7.
b. Review and approve CH-12, CH-13, CH-14, CH-15 for section 3.10
b. Finish review of 3.10 and through CH. 4.
clarification
problems
solutions
The first 11 chapters will be voted on with a single vote after reviewing
them.
There have been some email sent and I would like the senders to raise the
issues as we go through the appropriate chapters.
A copy of the LRM is available at:
<http://www.sutherland-hdl.com/download/SystemVerilog_3.1_draft1.pdf>
http://www.sutherland-hdl.com/download/SystemVerilog_3.1_draft1.pdf
5. Address any other issues before committee
Please review the information available on the website:
<http://www.eda.org/sv-ec> http://www.eda.org/sv-ec.
The documents, minutes, issues list, and enhancement lists are all available
there.
Please come prepared with questions and answers. Are time is getting short
and we have much to accomplish.
Regards
David
David W. Smith
Synopsys Scientist
Synopsys, Inc.
Synopsys Technology Park
2025 NW Cornelius Pass Road
Hillsboro, OR 97124
Voice: 503.547.6467
Main: 503.547.6000
FAX: 503.547.6906
Email: david.smith@synopsys.com
<http://www.synopsys.com/> http://www.synopsys.com
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