Subject: Re: [sv-ec] Comments on remainder of Chapter 3
From: Arturo Salz (Arturo.Salz@synopsys.com)
Date: Mon Jan 06 2003 - 12:20:21 PST
> 3.14 Dynamic casting
> --------------------
>
> Verilog uses have enough problems with static casting, this whole
> section seems unnecessary. I've seen this sort of programming construct
> in environments like GUI's where a user may have typed garbage in a
> field and you are trying to dynamically idiot proof the validation of
> the form, but I don't see why it is needed in Verilog.
>
> Where are dynamic casts needed?
Here's the relevant section of the message I previously sent.
Arturo
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4. Why is $cast_assign required for assigning a superclass instance to a derived class instance -
why is this not inherent in assignment?
A derived-class can be assigned directly to any of its super-classes. However, a super-class can
only be assigned to a derived class if and only if the sub-class is actually of that type. In general,
this can only be resolved at run-time, thus the need for a dynamic cast. For example:
class Animal { ... }
class Mammal extends Animal { ... }
class Dog extends Mammal { ... }
class Cat extends Mammal { ... }
Mammal m = new;
Animal a = m; // correct, mammal is an animal
Dog d = m; // error: m is not a dog
Cat c = d; // error: d is a dog not a cat
$cast_assign( d, m ); // allowed: triggers a run-time error
if( ! $cast_assign( d, m ) ) begin // user can check at run-time
d = new;
end
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