Subject: [sv-ec] Issues with Sections 7,8 & 10
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Fri Jan 10 2003 - 15:54:46 PST
7.3 (Last sentence)
>If functions f() and g() have side effects on variables a or b,
Verilog must enforce the left-to-right semantics to avoid the ambiguous
results.
Does that mean it always enforces it or just when there are side
efffects? Maybe it should say:
"Verilog enforces left-to-right evaluation in accordance with the
associativity to avoid the ambiguous results; functions f() and g() may
have side effects on variables a or b."
7.6
Should probably mention that ++/-- has no effect on reals if '1' is
below the available resolution.
8.7 (and 9.6)
Only the initial and always are static processes, fork/join creates
processes dynamically, and the label
refers to a group of processes in the case of a fork/join not an
individual process.
The process statement should return a process identifier.
10.5.2
Pass by reference should just use the C++ syntax e.g. "int &i" instead
of "var int i" - less typing
no new keywords and more polymorhic (i.e. less trouble using raw C/C++
code). Same goes for
any other usage of "var".
Kev.
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