Subject: RE: [sv-ec] Issues with Sections 7,8 & 10
From: David W. Smith (david.smith@synopsys.com)
Date: Fri Jan 10 2003 - 16:04:38 PST
Hi Kevin,
A couple of procedural points.
1. Section 7.6 has not been modified from 3.0. If there is an issue with it
I would appreciate it if you would bring it to the attention of the SV-BC.
2. Section 9.7 has been removed in the draft (as a suggestion). Likewise
section 8.7 should also have been removed. This was actually based on this
discussion on REV-15. If there are no objections then both sections are
gone.
This leaves your comments on Section 7.3 and 10.5.2 for discussion by the
committee.
Regards
David
-----Original Message-----
From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of Kevin
Cameron x3251
Sent: Friday, January 10, 2003 3:55 PM
To: sv-ec
Subject: [sv-ec] Issues with Sections 7,8 & 10
7.3 (Last sentence)
>If functions f() and g() have side effects on variables a or b,
Verilog must enforce the left-to-right semantics to avoid the ambiguous
results.
Does that mean it always enforces it or just when there are side
efffects? Maybe it should say:
"Verilog enforces left-to-right evaluation in accordance with the
associativity to avoid the ambiguous results; functions f() and g() may
have side effects on variables a or b."
7.6
Should probably mention that ++/-- has no effect on reals if '1' is
below the available resolution.
8.7 (and 9.6)
Only the initial and always are static processes, fork/join creates
processes dynamically, and the label
refers to a group of processes in the case of a fork/join not an
individual process.
The process statement should return a process identifier.
10.5.2
Pass by reference should just use the C++ syntax e.g. "int &i" instead
of "var int i" - less typing
no new keywords and more polymorhic (i.e. less trouble using raw C/C++
code). Same goes for
any other usage of "var".
Kev.
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