Subject: RE: [sv-ec] Re: discrete time
From: Jay Lawrence (lawrence@cadence.com)
Date: Wed Jan 15 2003 - 16:24:10 PST
Jayant,
I find this comment bizarre:
> Anyone who have implemented event simulator will know:
> Counting delta cycles and delta cycle semantics have been
> a big performance hinderance in VHDL simulators. We continue
> to have these VHDL wishes pushed on this discussions.
As you know, I do work on event simulators that handle both VHDL and
Verilog.
No performance concerns of VHDL stem from "Counting delta cycles", and
the "delta cycle semantics" are not a concept unique to VHDL, Verilog
has them too. This paranoia that continues around "VHDL has it so it
must be bad" has got to stop. I could start to argue that Java is the
slowest language on earth and Vera resembles Java, but I wouldn't stoop
so low.
I will freely admit that the non-determism and ambiguity of the
specification of Verilog provides opportunities for optimization that we
all exploit, but most of the performance comes from the basic predefined
data types and timing models that can be hightly optimized as opposed to
user-defined types and operators in VHDL.
Surely you are not suggesting that a world without delta cycles would
lead to further speedups and therefore all users should write fully
syncronous models AND testbenches. Pure cycle simulation as a simulation
accelleration technique has been pretty much been completely abandoned
by the industry. A few target markets (i.e. cpu design) can utilize it,
but the limited design style is crippling, especially when you try to
write a testbench! Our experience (and it appears the VCS experience as
well if our benchmark data is accurate) is that as the design becomes
more and more syncronous, and therefore possible to cycle simulate, the
event-simulator can speed up by just as much while still preserving the
event driven semantics and allowing the asyncronous portions to operate.
As a matter of fact, our experience is that the testbench is usually the
asyncronous part because it models THE REAL WORLD which, as Kevin C will
tell us all, is analog.
I'm unfamiliar with OVA, but very familiar with Sugar. It does a great
job of modeling syncronous and asyncronous behavior and can be simulated
very efficiently with results that are extremely consistent with formal
verification. There are issues when trying to get 100% correlation of
results. This would be exactly equivalent to attempting to define an HDL
which gets exactly the same simulation results pre- and post-synthesis
since both the formal methods and synthesis require a cycle accurate
view of the world. The industry has done a pretty good job to date of
creating modeling styles where simulation pre and post synthesis is
expected to correlate. These styles translate extremely well to formal
methods. If you stray outside them you have the same issues in both
techniques.
Jay
===================================
Jay Lawrence
Architect - Functional Verification
Cadence Design Systems, Inc.
(978) 262-6294
lawrence@cadence.com
===================================
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