Re: [sv-ec] Re: discrete time

Subject: Re: [sv-ec] Re: discrete time
From: Bernard Deadman (bdeadman@sdvinc.com)
Date: Wed Jan 15 2003 - 16:17:09 PST


Jayant,

1) I've read the proposed LRM, including the segment on assertions.  The assertion capability is contradictory, contains two quite dissimilar syntax's and is inferior to Sugar 2.0.  Worse still it's inadequate for the tasks I want to perform.  You'll convince me of it's suitability when you take the example properties developed as part of the process that selected Sugar and re-code ALL those using SystemVerilog assertions.

2) the second point is not directed specifically at you, but I previously commented:

I would also comment that the control (is this the correct term for a voluntary group?) of the OVA donation and its incorporation into SystemVerilog Assertions was comprehensively botched.  I was told:

From: Vassilios.Gerousis@infineon.com
Date: Tue, 18 Jun 2002 08:30:41 +0200

        As far as I am concerned Sugar will continue. Synopsys will provide special extensions for Sugar. Harry Foster will call a meeting to specifically consider this extension. This is part of the plans. The VFV committee will decide to accept or reject these extensions. But at least, Accellera can manage to unify the industry, rather than having two standards competing in the industry prior to DAC.


***HOW MUCH OF THIS HAPPENED????****   When did the consultation with the VFV committee take place?  What extensions were proposed for Sugar?


Sugar is a fine solution that meets requirements that are significantly more rigorous than the set to which you pointed me.  It's proven in the field.  Nobody has yet explained why the SV-AC committee even considered developing yet another syntax for Regular Expressions?  Is it simply that Sugar wasn't invented in Synopsys / Intel?  If there is a deficiency in Sugar, why haven't improvements been proposed to the VFV group when both Synopsys & Intel are (nominally at least) members of that committee?

Sorry, but I listened to lies at DAC, and I've seen a lot of foot shuffling since then.  Maybe I'm just an aging English cynic, but it seems to me like the only unification anyone is interested in here is the universal adoption of some as yet unproven but Synopsys inspired hybrid of Vera and Superlog.

What is it that scares everyone so much about capturing a full requirements spec. for the whole language, before trying to do the development work?

Regards

Bernard


At 03:52 PM 1/15/2003 -0800, Jayant Nagda wrote:
Bernard,

   It seems like you are selectively not aware of effort
   going in SV-AC's Design Working Group in unifying and creating
   single System Verilog Assertion language.

   Overall System Verilog will provide assertion capabilities
   for both simulation and formal tools which will be
   re-usable across tools.

   Anyone who have implemented event simulator will know:
   Counting delta cycles and delta cycle semantics have been
   a big performance hinderance in VHDL simulators. We continue
   to have these VHDL wishes pushed on this discussions.
 
   Instead any of us trying to educate you in responding to your
   mis statements and clarify your  confusions,  may we suggest that
   you read requirements for assertion and how SV-AC is
   addressing those requirements : http://www.eda.org/sv-ac/hm ?
 
Jayant Nagda

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