Subject: [sv-ec] Timeunit proposal
From: Francoise Martinolle (fm@cadence.com)
Date: Wed Jan 15 2003 - 19:34:34 PST
Dave,
There is a rule onm verilog which says that if there is a timescale
directive for one module, a timescale must be specified for every module
in the design.
Is there such a rule for the declarations?
Francoise
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