Subject: Re: [sv-ec] Timeunit proposal
From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Thu Jan 23 2003 - 09:26:13 PST
At 10:34 PM 1/15/03 -0500, Francoise Martinolle wrote:
>Dave,
>
>There is a rule onm verilog which says that if there is a timescale
>directive for one module, a timescale must be specified for every module
>in the design.
>Is there such a rule for the declarations?
>Francoise
There is no such rule, but if there are timescales in the design, every
simulator I have used requires that the first module include a timescale;
otherwise, the simulator assumes either a default timescale or just uses
integer unit delays until a timescale directive is found, then the
simulator complains bitterly to the user that the rules for time delays
have changed.
If the first module compiled uses a timescale (such as a testbench), then
theoretically you don't need a timescale anywhere else in the design. My
guideline is to add a timescale to any module that has #-delays and leave
it off of other modules.
Does this answer your question or was I missing the point?
Regards - Cliff
----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
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