Subject: Re: [sv-ec] Re: [sv-bc] Packed arrays
From: Steven Sharp (sharp@cadence.com)
Date: Thu Jan 30 2003 - 11:30:29 PST
> >Date: Wed, 29 Jan 2003 17:35:52 -0800 (PST)
>> >From: "Kevin Cameron x3251" <Kevin.Cameron@nsc.com>
>>
>> >The conversion isn't the issue, it's the propagation as bits. Sure you
>> >can spend a lot of time optimizing it all away, but it's cheaper just
>> >to specify it as a shared real value if that's what you want.
It occurs to me that you might think that a 64-bit vector wire will get
propagated as 64 one-bit wires with strength on each. That would indeed
be slower. The SV spec tries to imply that Verilog does this, to claim
superiority for its own "logic" type. In fact, any reasonable Verilog
simulator will represent a vector net as a single object, with the same
encoding that the logic type uses. Vectors only get expanded when certain
conditions require it, and none of those should apply in this situation.
So using $realtobits to transfer real numbers over a vector net is not
significantly less efficient than an AMS wreal.
Steven Sharp
sharp@cadence.com
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