Subject: Re: [sv-ec] Re: [sv-bc] Packed arrays
From: Steven Sharp (sharp@cadence.com)
Date: Thu Jan 30 2003 - 11:43:37 PST
>Packed structs are equivalent to bit vectors, each bit (maybe) representing
>a seperate physical wire. What I want to say is that a bundle of 64 wires can
>be carrying a double or an integer or some other bit pattern.
SV doesn't allow struct types for nets, only variables. It doesn't matter
whether the struct is packed or not. So allowing reals in packed structs
has no effect on whether you can carry them on vector nets.
If you are saying that you think it should be possible to have a vector net
that carries a packed struct, then I agree with you. But that is a separate
issue from whether reals should be allowed in packed structs.
>It allows you to prefix any struct with "packed" and get a well defined
>behavior rather than a compiler error, and lets you describe busses with
>floating point fields (useful in a debugger if nothing else).
The Verilog language already puts a lot of restrictions on reals that
amount to a design philosophy that reals should not be treatable as a
vector of bits. I haven't heard of anyone chafing over this.
Steven Sharp
sharp@cadence.com
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