Subject: Re: [sv-ec] Re: [sv-bc] Packed arrays
From: Steven Sharp (sharp@cadence.com)
Date: Fri Jan 31 2003 - 14:19:55 PST
>There doesn't appear to be a good reason why you can't connect packed structs
>through ports to me, but I don't need to since I can put the struct in an
>interface and share it that way.
Which may be sufficient for your needs. However, variables shared via an
interface don't provide all the capabilities that HW designers get with nets:
things like driver resolution, net delays, path delays, interconnect delays
and SDF back annotation.
>Well, since people build hardware that processes reals as well as ints I see
>no reason for making a distinction.
>
>How would you describe a bus carrying a double value as well as other values?
As Mac pointed out, HW designers don't build hardware that processes reals.
They build hardware that processes the bits that represent floating point
numbers in the format that their hardware is designed for.
If someone is working with Verilog reals as data, they are working with
abstractions. There is no reason to require that they be mapped to a
particular hardware representation as a vector of bits. So there is no
reason to require them to be allowed in a packed struct. And if they were
allowed in a packed struct, there would be no reason to require a particular
bit layout.
If I was working with an abstraction that I wanted to be able to use to
hold/carry a real as well as other values, I would use a non-packed struct.
Steven Sharp
sharp@cadence.com
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