Subject: [sv-ec] Agenda for meeting on 3 February 2003
From: David W. Smith (david.smith@synopsys.com)
Date: Fri Jan 31 2003 - 14:20:25 PST
There will be an extra meeting for the SV-EC committee from 11:00am until
1:00pm PDT on Monday 3 February 2003.
Meeting will start promptly at 11:00am and may run over in order to complete
review of all three chapters.
Dial in Information
* PARTICIPANT CODE: 516134
* Toll Free Dial In Number: (877)233-7845
* International Access/Caller Paid Dial In Number: (505)766-5458
Agenda
1. Review and approve minutes from Jan 27 meeting
2. Review and resolve email voting results (CH-34 and CH-36 in particular,
see attached)
3. Review open Action Items (see Action Item list at
<http://www.eda.org/sv-ec/ActionItems.html>
http://www.eda.org/sv-ec/ActionItems.html)
Items AI-1, 2, 4, 5, 8, 9, 10, 12, 13, 14, 15, 16, 41 have been closed
with new change requests as appropriate.
4. Approve Changes:
CH-23, CH-33, CH-43, CH-59, CH-66, CH-67, CH-70 through CH-82
These are all either changes done before Draft 2 or the result of action
items that have been completed.
The vote will be done as follows:
a. Request any issues with the listed changes
b. For those changes with no issues they will be voted on as a group
c. For those changes with issues they will be discussed and resolved
(with either vote or a change to the item).
4. Vote on process/thread spawning options: 2 items to vote on (See attached
document)
5. Review LRM
a. Review 10.1, 10.3.2, 10.4, 10.5, 11, 12
b. Vote on acceptance of Chapters 1-11, 12 (with condition that all
relate action items will be approved)
6. Address any other issues before committee
For the rest of the review process discussion will be limited to the
following items:
clarification
problems
solutions to clarification and problems
No new proposals will be entertained.
A copy of the LRM is available at:
< <http://www.sutherland-hdl.com/download/SystemVerilog_3.1_draft1.pdf>
http://www.sutherland-hdl.com/download/SystemVerilog_3.1_draft1.pdf>
<http://www.sutherland-hdl.com/download/SystemVerilog_3.1_draft1.pdf>
http://www.sutherland-hdl.com/download/SystemVerilog_3.1_draft1.pdf
Please review the information available on the website:
< <http://www.eda.org/sv-ec> http://www.eda.org/sv-ec>
<http://www.eda.org/sv-ec> http://www.eda.org/sv-ec.
David W. Smith
Synopsys Scientist
Synopsys, Inc.
Synopsys Technology Park
2025 NW Cornelius Pass Road
Hillsboro, OR 97124
Voice: 503.547.6467
Main: 503.547.6000
FAX: 503.547.6906
Email: david.smith@synopsys.com
<http://www.synopsys.com/> http://www.synopsys.com
This archive was generated by hypermail 2b28 : Fri Jan 31 2003 - 14:22:08 PST