Subject: Re: [sv-ec] fork join proposal
From: Stefen Boyd (stefen@boyd.com)
Date: Mon Feb 03 2003 - 10:03:07 PST
I was surprised to see option #4. The fourth
option was supposed to be:
all fork...join
any fork...join(expression) // where expression == 1
none fork...join(expression) // where expression == 0
The constant substituted for keyword was a wacky idea, but
was good brainstorming for something reasonable. If it needs
to be limited to a constant expression, fine, but this is
a reasonable proposal, while the option 4 is silly. This
is what was *supposed* to be option 4!
Stefen
At 09:21 AM 2/3/2003 -0500, Francoise Martinolle wrote:
>A comment
>
>In the fork join proposal, there are now 2 ways to create a fork join with
>the
>previous Verilog semantics. For example with option 2 fork join_all and
>fork join
>are 2 ways to create a fork-join all.
>
>we could get rid of the all and -1 so that we use the Verilog fork join
>because it is
>already the way people use it and I doubt they will be using it with
>adding "all".
>
>At 02:20 PM 1/31/2003 -0800, David W. Smith wrote:
>
>>There will be an extra meeting for the SV-EC committee from 11:00am until
>>1:00pm PDT on Monday 3 February 2003.
>>
>>Meeting will start promptly at 11:00am and may run over in order to
>>complete review of all three chapters.
>>
>>Dial in Information
>>
>>* PARTICIPANT CODE: 516134
>>* Toll Free Dial In Number: (877)233-7845
>>* International Access/Caller Paid Dial In Number: (505)766-5458
>>
>>Agenda
>>
>>1. Review and approve minutes from Jan 27 meeting
>>2. Review and resolve email voting results (CH-34 and CH-36 in
>>particular, see attached)
>>3. Review open Action Items (see Action Item list at
>><http://www.eda.org/sv-ec/ActionItems.html>http://www.eda.org/sv-ec/ActionItems.html)
>> Items AI-1, 2, 4, 5, 8, 9, 10, 12, 13, 14, 15, 16, 41 have been
>> closed with new change requests as appropriate.
>>4. Approve Changes:
>> CH-23, CH-33, CH-43, CH-59, CH-66, CH-67, CH-70 through CH-82
>> These are all either changes done before Draft 2 or the result of
>> action items that have been completed.
>> The vote will be done as follows:
>> a. Request any issues with the listed changes
>> b. For those changes with no issues they will be voted on as a group
>> c. For those changes with issues they will be discussed and
>> resolved (with either vote or a change to the item).
>>
>>4. Vote on process/thread spawning options: 2 items to vote on (See
>>attached document)
>>5. Review LRM
>> a. Review 10.1, 10.3.2, 10.4, 10.5, 11, 12
>> b. Vote on acceptance of Chapters 1-11, 12 (with condition that all
>> relate action items will be approved)
>>
>>6. Address any other issues before committee
>>For the rest of the review process discussion will be limited to the
>>following items:
>>clarification
>>problems
>>solutions to clarification and problems
>>
>>No new proposals will be entertained.
>>
>>A copy of the LRM is available at:
>>
>><<http://www.sutherland-hdl.com/download/SystemVerilog_3.1_draft1.pdf>http://www.sutherland-hdl.com/download/SystemVerilog_3.1_draft1.pdf>
>>
>>http://www.sutherland-hdl.com/download/SystemVerilog_3.1_draft1.pdf
>>
>>Please review the information available on the website:
>> <<http://www.eda.org/sv-ec>http://www.eda.org/sv-ec>
>> http://www.eda.org/sv-ec.
>>
>>David W. Smith
>>Synopsys Scientist
>>
>>Synopsys, Inc.
>>Synopsys Technology Park
>>2025 NW Cornelius Pass Road
>>Hillsboro, OR 97124
>>
>>Voice: 503.547.6467
>>Main: 503.547.6000
>>FAX: 503.547.6906
>>Email: <mailto:david.smith@synopsys.com>david.smith@synopsys.com
>>http://www.synopsys.com
>>
>
>--------------------
>Stefen Boyd Boyd Technology, Inc.
>stefen@BoydTechInc.com (408)739-BOYD
>www.BoydTechInc.com (408)739-1402 (fax)
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