Subject: RE: [sv-ec] Email vote on var usage
From: Jay Lawrence (lawrence@cadence.com)
Date: Tue Feb 04 2003 - 14:42:56 PST
Mac,
Just to make sure you know what your expressing an interest on. This is
not to actually take a reference (i.e. address of) an object. This is
just to declare in a task or function argument list that the object
should be passed by reference.
There is still no address of operator in SystemVerilog (thank god).
Jay
===================================
Jay Lawrence
Architect - Functional Verification
Cadence Design Systems, Inc.
(978) 262-6294
lawrence@cadence.com
===================================
> -----Original Message-----
> From: Michael McNamara [mailto:mac@verisity.com]
> Sent: Tuesday, February 04, 2003 5:39 PM
> To: Stefen Boyd
> Cc: David W. Smith; sv-ec@eda.org
> Subject: Re: [sv-ec] Email vote on var usage
>
>
>
> Stefen Boyd writes:
> > [1 <text/plain; us-ascii (7bit)>]
> > At 05:04 PM 2/3/2003 -0800, David W. Smith wrote:
> > > __yes _x_no var
> > > __yes _x_no ref (substitute use of var with ref)
> > > _x_yes __no & (substitute use of var with & and
> move the use to
> > > just before the argument name - instead of before the type)
> >
> > --------------------
> > Stefen Boyd Boyd Technology, Inc.
> > stefen@BoydTechInc.com (408)739-BOYD
> > www.BoydTechInc.com (408)739-1402 (fax)
> > [2 <text/html; us-ascii (7bit)>]
> >
>
> I know I am not eligiable to vote, but I endorse the use of '&' in
> indicate taking a reference.
>
> -mac
>
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