Subject: [sv-ec] RE: [sv-ac] syntax: compatibility with verilog and other issues
From: Jay Lawrence (lawrence@cadence.com)
Date: Tue Feb 11 2003 - 01:22:03 PST
Cindy,
The issue is more general than that, the sv-ec has not come to a
consensus opinion yet and if you ask any one member you'll get different
answers. I will do my best not to express an opinion, but bring the
sv-ac up to speed on the sv-ec status on this topic. David Smith should
certainly clarify if I mis-state anything.
The sv-ec is working through the Draft LRM (we currently use Draft 2)
sequentially beginning in Chapter 1 and working forward. When discussing
the event data type in Section 3.8, a heated debate began around the
meaning of and necessity for the new "persistent event". This debate
inevitably began to discuss the $wait_* system tasks defined in Section
12.6 - 12.9 which give the events their semantics. Although the debate
continued on email for a few days (weeks), the sv-ec decided to simply
postpone further discussion of the Event data type declaration until the
semantics of it could be discussed in Section 12. We made a similar
decision to skip the declaration of classes in Section 3.12 until
discussion of Section 11 which is a whole section devoted to classes.
The current review status is that yesterday we had an sv-ec meeting
where we got about 1/2 of the way through Section 11 (11.13 to be
precise). We are hoping to get through the rest of 11 and Section 12 in
the next meeting, but since we haven't gotten up to Section 12 yet,
there has been no official vote on the semantics of persistent events or
the syncronization operators. Hence, no official sv-ec stance.
**** Note: The following may be straying into opinion ****
So the basic question to both committees is:
Are the Event syncronization semantics which allow waiting on a single
event, multiple events, or an ordered list of events, the same semantics
as the sequence capability of a property?
If yes, then we should utilize a common syntax. This would probably
allow a sequence to follow an '@' or 'wait' statement in procedural code
and have the same scheduling behavior as scheduling evaluation of the
property.
If not, then we should utilize a different syntax to make it clear they
are different.
I assume this is another one of the cross-group issues that is probably
best worked out with a working group between the different committees.
Jay
===================================
Jay Lawrence
Architect - Functional Verification
Cadence Design Systems, Inc.
(978) 262-6294
lawrence@cadence.com
===================================
> -----Original Message-----
> From: Cindy Eisner [mailto:EISNER@il.ibm.com]
> Sent: Tuesday, February 11, 2003 3:43 AM
> To: Kevin Cameron x3251
> Cc: sv-ac@eda.org
> Subject: Re: [sv-ac] syntax: compatibility with verilog and
> other issues
>
>
> kevin,
>
> thanks for your response, but i didn't understand. you say:
>
> >I don't think the EC is waiting on any particular decision,
> it would just
> >be nice to have consistent syntax.
>
> i agree. but i don't know what your definition of
> "consistent" is. it can
> go either way:
>
> definition 1 of consistent: the current use of "or" in
> verilog is only for
> event expressions, therefore consistency demands keeping it so.
> definition 2 of consistent: "or" is already used in verilog to
> distinguish between or'ing of events and or'ing of vars and
> regs, therefore
> consistency demands using it to distinguish as well between or'ing of
> sequences and or'ing of vars and regs.
>
> please say if you have a strong opinion on which definition
> is better, or
> if you have another definition of "consistent" in mind.
>
> thanks,
>
> cindy.
>
> Cindy Eisner
> Formal Methods Group Tel:
> +972-4-8296-266
> IBM Haifa Research Laboratory Fax: +972-4-8296-114
> Haifa 31905, Israel e-mail:
> eisner@il.ibm.com
>
>
> "Kevin Cameron x3251" <Kevin.Cameron@nsc.com> on 10/02/2003 19:16:06
>
> To: Cindy Eisner/Haifa/IBM@IBMIL
> cc: sv-ac@eda.org
> Subject: Re: [sv-ac] syntax: compatibility with verilog
> and other issues
>
>
>
> > From: "Cindy Eisner" <EISNER@il.ibm.com>
> >
> > kevin,
> >
> > >> 1. proposal: move to more verilog-like syntax: "&"
> for "and", "|"
> for
> > >> "or", etc.
> > >
> > >'or' is already there for event expressions.
> >
> > yes, but in my mind an event expression is an entirely
> different animal.
> >
>
> I was just saying the use of "and" had been suggested elsewhere.
>
> > >The EC did have a short
> > >discussion about adding other operators -
> > >
> > > http://www.eda.org/sv-ec/hm/0386.html (follow thread)
> > >
> > >I think the EC is waiting to see if the AC covered this
> kind of thing to
> > >avoid having different syntax for event expressions/sequences.
> >
> > not sure what you mean here. i didn't follow the whole
> thread you point
> to
> > above, but mike mcnamara seemed to make a very strong point
> that allowing
> > "and" as an event control wouldn't make a lot of sense.
> can you explain
> > exactly what decision the ec is waiting on, and what the
> implications
> are?
>
> "and" makes sense if you are using "persistent" events
> (normal events don't
> overlap).
>
> I don't think the EC is waiting on any particular decision,
> it would just
> be nice to have consistent syntax.
>
> > >IMO it's easier for users if you use different operators for event
> > >expressions WRT reading other peoples code.
> >
> > yes, i agree. i think that event expressions are very
> different than
> > logical expressions, and the syntax of the language should
> make a strong
> > distinction between them.
> >
> > cindy.
>
> Kev.
>
> > Cindy Eisner
> > Formal Methods Group Tel:
> +972-4-8296-266
> > IBM Haifa Research Laboratory Fax: +972-4-8296-114
> > Haifa 31905, Israel e-mail:
> > eisner@il.ibm.com
> >
> >
> > "Kevin Cameron x3251" <Kevin.Cameron@nsc.com> on 06/02/2003 19:45:09
> >
> > To: sv-ac@eda.org, Cindy Eisner/Haifa/IBM@IBMIL
> > cc:
> > Subject: Re: [sv-ac] syntax: compatibility with verilog and other
> issues
> >
> >
> >
> > > From: "Cindy Eisner" <EISNER@il.ibm.com>
> > >
> > >
> > > all,
> > >
> > > i would like to raise the issue of syntactical compatibility with
> > verilog.
> > > i find the introduction of vhdl-like keywords "and",
> "or", etc. very
> > > jarring. therefore, i propose that
> > >
> > > 1. proposal: move to more verilog-like syntax: "&" for
> "and", "|"
> for
> > > "or", etc.
> >
> > 'or' is already there for event expressions. The EC did have a short
> > discussion about adding other operators -
> >
> > http://www.eda.org/sv-ec/hm/0386.html (follow thread)
> >
> > I think the EC is waiting to see if the AC covered this
> kind of thing to
> > avoid having different syntax for event expressions/sequences.
> >
> > IMO it's easier for users if you use different operators for event
> > expressions WRT reading other peoples code.
> >
> > Kev.
> >
> > > also, i would like to see a short-hand for a sequential
> implication in
> > > which the right-hand side starts a cycle after the left-hand side
> > > completes. today, we have:
> > >
> > > (a;b;c) => (d;e;f)
> > >
> > > which means that if we see a followed by b followed by c, then we
> should
> > > see d followed by e followed by f, and d must happen the
> cycle of c.
> to
> > > say something similar, but where (d;e;f) starts the cycle
> *after* c, we
> > > must today say:
> > >
> > > (a;b;c) => (true;d;e;f)
> > >
> > > if we eliminate the "true", as some have requested, then
> we have to say
> > >
> > > (a;b;c) => (1;d;e;f)
> > >
> > > or use a leading delay. i think that a delay of one is a
> very common
> > > situation, and would like to see a short-cut syntax for
> it. in psl we
> > > have:
> > >
> > > |-> sequence implication where right-hand side starts the
> cycle the
> > > left-hand side ends
> > > |=> sequence implication where right-hand side starts the
> cycle after
> the
> > > left-hand side ends
> > >
> > > i would like to see a similar idea in sv. therefore, i
> propose that
> > >
> > > 2. proposal: add a sequence implication operator which
> requires the
> > > right-hand side to start a cycle after the left-hand side
> > >
> > > note that i have not specificed a syntax. of course, i
> prefer "|->"
> and
> > "
> > > |=>" as in psl.
> > >
> > > regards,
> > >
> > > cindy.
> > >
> > > Cindy Eisner
> > > Formal Methods Group Tel:
> +972-4-8296-266
> > > IBM Haifa Research Laboratory Fax: +972-4-8296-114
> > > Haifa 31905, Israel
> e-mail:
> > > eisner@il.ibm.com
> > >
> > >
> > >
> >
> >
> >
> >
> >
> >
> >
>
>
>
>
>
>
This archive was generated by hypermail 2b28 : Tue Feb 11 2003 - 01:23:09 PST