Subject: RE: [sv-ec] Section 10.4 task/fun lifetime
From: David W. Smith (david.smith@synopsys.com)
Date: Sun Mar 09 2003 - 18:24:30 PST
See AI-46 for your first issue (it is in progress).
Strictly speaking the attribute is not added in SystemVerilog for program
(since program did not exist in Verilog). The paragraph states that the
lifetime attribute for the program block is defined in Section 15. I think
that it is clear the way it is.
Regards
David
David W. Smith
Synopsys Scientist
Synopsys, Inc.
Synopsys Technology Park
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Hillsboro, OR 97124
Voice: 503.547.6467
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Email: david.smith@synopsys.com
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-----Original Message-----
From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of Stefen
Boyd
Sent: Wednesday, March 05, 2003 3:21 PM
To: david Smith
Cc: sv-ec@eda.org
Subject: [sv-ec] Section 10.4 task/fun lifetime
David,
I remember that when going through this section we made the lifetime of
tasks and functions the same in programs and modules. I couldn't find it in
your change list, though, and that change hasn't made it into the draft3
document. What happened?
Also, it mentions "module attribute" in the first sentence of the second
paragraph. Since the last paragraph mentions program, it might be clear that
it's not just for modules. It should probably say "module, program, and
interface".
Stefen
--------------------
Stefen Boyd Boyd Technology, Inc.
stefen@BoydTechInc.com (408)739-BOYD
www.BoydTechInc.com (408)739-1402 (fax)
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