Subject: Re: [sv-ec] Event Proposal
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Mon Mar 10 2003 - 10:27:06 PST
----------
X-Sun-Data-Type: text
X-Sun-Data-Description: text
X-Sun-Data-Name: text
X-Sun-Charset: us-ascii
X-Sun-Content-Lines: 178
> From: "Arturo Salz" <Arturo.Salz@synopsys.com>
>
> Francoise,
>
> Thanks for the comments.
>
> The $wait_all and $wait_any and $wait_order are shorthand notations for the following:
>
> $wait_all( a, b, c )
>
> fork
> wait( a.triggered ); wait( b.triggered ); wait( c.triggered );
> join
>
> $wait_any( a, b, c )
>
> wait( a.triggered || b.triggered || c.triggered );
>
> $wait_order( a, b, c )
>
> reg abc[1:3] = '0;
> fork
> begin wait( a.triggered ); abc[1] = 1; if( abc != '100 ) $error; end
> begin @b; abc[2] = 1; if( abc != '110 ) $error; end
> begin @c; abc[3] = 1; if( abc != '111 ) $error; end
> join_none
>
> As for enhancing the other operators, that approach seemed to be rather
> controversial and we were unable to reach consensus. I'd prefer to keep
> the enhancement simple so that we can all agree.
>
> Arturo
Since these functions are only "shorthand" (i.e. no functionality is missing) would
it not be better to leave them out for now and reconsider the shorthand syntax
with respect to the assertion sequences for 3.2 and/or provide any missing mechanisms
that prevent users doing this themselves in tasks? (or putting them in a standard
include file)
Regards,
Kev.
> ----- Original Message -----
> From: "Francoise Martinolle" <fm@cadence.com>
> To: "Arturo Salz" <Arturo.Salz@synopsys.COM>
> Cc: <sv-ec@eda.org>
> Sent: Monday, March 10, 2003 8:07 AM
> Subject: Re: [sv-ec] Event Proposal
>
>
> Arturo,
>
> I like this proposal better.
> I suggest that for clarification the definition of $wait_all and $wait_any,
> $wait_order,
> is also described in terms of semantically equivalent verilog code.
>
> Note: I am not sure if I have the correct equivalent description. But this
> is just provided
> as an example.
> Ex:
> $wait_all(a, b);
> <stmt>;
> creates a single process equivalent to:
>
> equivalent to:
> rega = 1'b0; initialize the state of a and b
> regb = 1'b0;
>
> initial(@a or @b)
> if (a.triggered)
> rega = 1'b1;// state that a has triggered
> already once
> if (a.triggered) || (rega == 1'b1) { // a
> triggered now or has triggered before
> @b;
> }
> if (b.triggered)
> regb = 1'b1;// state that b has triggered
> already once
> if ((b.triggered) || (regb == 1'b1))
> @a;
> <stmt>
> rega = 1'b0; // reset rega and regb
> regb = 1'b0;
> end
>
> $wait_any(a,b);
> <stmt>;
> creates a single process equivalent to
> @(a or b) <stmt>;
>
> $wait_order(a, b);
> <stmt>
> creates a single process equivalent to:
> rega = 1'b0;
> initial (@a or @b)
> if (a.triggered) {
> rega = 1'b1;
> @b;
> <stmt>
>
> }
> if (b.triggered && (!rega))
> error;
>
> end
>
> I also think that another alternative is to enhance the wait statement
> defined in section 9.7.6
> in the Verilog 1364 LRM instead of introducing new built in system tasks
>
> For example:
> wait (@a or @b); would wait on either a or b events to trigger;
> equivalent to $wait_any(a, b)
> wait ((@a or a.triggered) and (@b or b.triggered)); would wait on both
> a and b events to
> trigger
> in any order ;
> In order to wait across multiple simulation steps, you have to
> introduce a new operator to
> tell you that the execution will not continue until the condition
> expression "until" becomes
> true. The wait statement waits for the first condition expression to
> become true and
> then blocks again until the until expression becomes true.
>
> wait ((@a and @b) or (@a until b.triggered) or ( (@b until a.triggered));
> equivalent
> to $wait_all(a, b)
>
> wait (@a);
> wait (@b): would wait on a event to trigger then b event to trigger;
> equivalent to $wait_order(a, b);
>
>
> Francoise
> '
>
> At 04:25 PM 3/7/2003 -0800, Kevin Cameron wrote:
>
>
> >Arturo Salz wrote:
> >
> > > Attached is a new proposal for event (and the differences with the last
> > draft).
> > >
> > > Arturo
> >
> >Definitely better :-)
> >
> >However I notice we're still not differentiating events and event
> >references - sec 12.8.
> >I would prefer to drop 12.8 and just use references to events for the
> >extra functionality
> >e.g.:
> > event ref ER = null;
> > event E;
> > ....
> > -> ER; // NOP
> > ....
> > ER = E;
> > ...
> > -> ER; // same -> E
> >
> >- more or less the same functionality but I think it would be clearer to
> >users.
> >
> >Regards,
> >Kev.
> >
> >
> >--
> >National Semiconductor, Tel: (408) 721 3251
> >2900 Semiconductor Drive, Mail Stop D3-500, Santa Clara, CA 95052-8090
>
----------
X-Sun-Data-Type: html
X-Sun-Encoding-Info: quoted-printable
X-Sun-Content-Length: 13301
X-Sun-Content-Lines: 270
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 5.50.4807.2300" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY>
<DIV><FONT face=3DArial size=3D2>Francoise,</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>Thanks for the comments.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>The $wait_all and $wait_any and =
$wait_order are=20
shorthand notations for the following:</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2><U>$wait_all( a, b, c =
)</U></FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2> fork</FONT></DIV>
<DIV><FONT face=3DArial size=3D2> =
wait(=20
a.triggered ); wait( b.triggered ); wait( c.triggered ); </FONT></DIV>
<DIV><FONT face=3DArial size=3D2> </FONT>join</DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2><FONT face=3DArial =
size=3D2><U>$wait_any( a, b, c=20
)</U></FONT></DIV>
<DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV> wait( a.triggered || b.triggered || c.triggered =
);</DIV>
<DIV> </DIV>
<DIV>
<DIV><FONT face=3DArial size=3D2><U>$wait_order( a, b, c =
)</U></FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2> reg =
abc[1:3] =3D=20
'0;</FONT></DIV>
<DIV><FONT face=3DArial size=3D2> fork</FONT></DIV>
<DIV><FONT face=3DArial size=3D2> =
begin wait(=20
a.triggered ); abc[1] =3D 1; if( abc !=3D '100 ) $error; =
end</FONT></DIV>
<DIV><FONT face=3DArial size=3D2> =
begin @b;=20
abc[2] =3D 1; if( abc !=3D '110 ) $error; end</FONT></DIV>
<DIV> begin @c; abc[3] =3D 1; if( =
abc !=3D '111=20
) $error; end</DIV>
<DIV><FONT face=3DArial size=3D2> =
</FONT>join_none</DIV>
<DIV> </DIV>
<DIV>As for enhancing the other operators, that approach seemed to be=20
rather</DIV>
<DIV>controversial and we were unable to reach consensus. I'd prefer to=20
keep</DIV>
<DIV>the enhancement simple so that we can all agree.</DIV>
<DIV> </DIV>
<DIV> Arturo</DIV>
<DIV> </DIV></DIV></FONT></DIV>
<DIV><FONT face=3DArial size=3D2>----- Original Message ----- </FONT>
<DIV><FONT face=3DArial size=3D2>From: "Francoise Martinolle" =
<</FONT><A=20
href=3D"mailto:fm@cadence.com"><FONT face=3DArial=20
size=3D2>fm@cadence.com</FONT></A><FONT face=3DArial =
size=3D2>></FONT></DIV>
<DIV><FONT face=3DArial size=3D2>To: "Arturo Salz" <</FONT><A=20
href=3D"mailto:Arturo.Salz@synopsys.COM"><FONT face=3DArial=20
size=3D2>Arturo.Salz@synopsys.COM</FONT></A><FONT face=3DArial=20
size=3D2>></FONT></DIV>
<DIV><FONT face=3DArial size=3D2>Cc: <</FONT><A =
href=3D"mailto:sv-ec@eda.org"><FONT=20
face=3DArial size=3D2>sv-ec@eda.org</FONT></A><FONT face=3DArial=20
size=3D2>></FONT></DIV>
<DIV><FONT face=3DArial size=3D2>Sent: Monday, March 10, 2003 8:07 =
AM</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>Subject: Re: [sv-ec] Event=20
Proposal</FONT></DIV></DIV>
<DIV><FONT face=3DArial><BR><FONT size=3D2></FONT></FONT></DIV><FONT =
face=3DArial=20
size=3D2>Arturo,<BR><BR>I like this proposal better.<BR>I suggest that =
for=20
clarification the definition of $wait_all and $wait_any, =
<BR>$wait_order,<BR>is=20
also described in terms of semantically equivalent verilog =
code.<BR><BR>Note: I=20
am not sure if I have the correct equivalent description. But this =
<BR>is just=20
provided<BR>as an example.<BR>Ex:<BR>$wait_all(a,=20
b);<BR><stmt>;<BR>creates a single process equivalent=20
to:<BR><BR>equivalent=20
to:<BR> =
=
rega =3D 1'b0; initialize the state of a and=20
b<BR> &n=
bsp; =20
regb =3D=20
1'b0;<BR><BR> =
&=
nbsp;=20
initial(@a or=20
@b)<BR> =
&=
nbsp; =20
if=20
(a.triggered)<BR> &n=
bsp; &nb=
sp; =20
rega =3D 1'b1;// state that a has triggered <BR>already=20
once<BR>  =
; =
=20
if (a.triggered) || (rega =3D=3D 1'b1) { // a <BR>triggered now or =
has=20
triggered=20
before<BR> &nb=
sp; &nbs=
p; =20
@b;<BR> =
&=
nbsp; =20
}<BR> &n=
bsp; &nb=
sp; =20
if=20
(b.triggered)<BR> &n=
bsp; &nb=
sp; =20
regb =3D 1'b1;// state that b has triggered <BR>already=20
once<BR>  =
; =
=20
if ((b.triggered) || (regb =3D=3D=20
1'b1))<BR> &nb=
sp; &nbs=
p; =20
@a;<BR> =
&=
nbsp; =20
<stmt><BR> &nb=
sp; &nbs=
p; =20
rega =3D 1'b0; // reset rega and=20
regb<BR>  =
; =
=20
regb =3D=20
1'b0;<BR> &nbs=
p;  =
;=20
end<BR><BR>$wait_any(a,b);<BR><stmt>;<BR>creates a single process=20
equivalent=20
to<BR> &=
nbsp; =20
@(a or b) <stmt>;<BR><BR>$wait_order(a, =
b);<BR><stmt><BR>creates a=20
single process equivalent=20
to:<BR> =
=20
rega =3D=20
1'b0;<BR> &nbs=
p; =20
initial (@a or=20
@b)<BR> =
&=
nbsp; =20
if (a.triggered)=20
{<BR> &n=
bsp; &nb=
sp; =20
rega =3D=20
1'b1;<BR> &nbs=
p;  =
; =20
@b;<BR> =
&=
nbsp; =20
<stmt><BR><BR>  =
; =
=20
}<BR> &n=
bsp; &nb=
sp; =20
if (b.triggered &&=20
(!rega))<BR> &=
nbsp; &n=
bsp; =20
error;<BR><BR>  =
; =
=20
end<BR><BR>I also think that another alternative is to enhance the wait=20
statement <BR>defined in section 9.7.6<BR>in the Verilog 1364 LRM =
instead of=20
introducing new built in system tasks<BR><BR>For =
example:<BR> =20
wait (@a or @b); would wait on either a or b events to=20
trigger;<BR> &=
nbsp; &n=
bsp; =20
equivalent to $wait_any(a, b)<BR> wait ((@a or =
a.triggered)=20
and (@b or b.triggered)); would wait on both <BR>a and b events=20
to<BR> &=
nbsp; &n=
bsp; &nb=
sp; &nbs=
p;  =
; =
=20
trigger <BR>in any order ;<BR> In order to wait across =
multiple simulation steps, you have to <BR>introduce a new operator=20
to<BR> tell you that the execution will not continue =
until the=20
condition <BR>expression "until" becomes<BR> true. The wait=20
statement waits for the first condition expression to <BR>become true=20
and<BR> then blocks again until the until expression becomes =
true.<BR><BR> wait ((@a and @b) or (@a until =
b.triggered) or (=20
(@b until=20
a.triggered));<BR> &=
nbsp; &n=
bsp; &nb=
sp; &nbs=
p;  =
; =
=20
equivalent <BR>to $wait_all(a, b)<BR><BR> wait=20
(@a);<BR> wait (@b): would wait on a event to trigger =
then b=20
event to=20
trigger;<BR> &=
nbsp; =20
equivalent to $wait_order(a,=20
b);<BR><BR><BR>Francoise<BR> =20
'<BR><BR>At 04:25 PM 3/7/2003 -0800, Kevin Cameron =
wrote:<BR><BR><BR>>Arturo=20
Salz wrote:<BR>><BR>> > Attached is a new proposal for event =
(and the=20
differences with the last <BR>> draft).<BR>> ><BR>>=20
> Arturo<BR>><BR>>Definitely better=20
:-)<BR>><BR>>However I notice we're still not differentiating =
events and=20
event <BR>>references - sec 12.8.<BR>>I would prefer to drop 12.8 =
and just=20
use references to events for the <BR>>extra=20
functionality<BR>>e.g.:<BR>> &nb=
sp; =20
event ref ER =3D =
null;<BR>> =20
event E;<BR>> =20
....<BR>> -> ER; =
//=20
NOP<BR>> =20
....<BR>> ER =3D=20
E;<BR>> =20
...<BR>> -> ER; // =
same -> E<BR>><BR>>- more or less the same functionality =
but I=20
think it would be clearer to=20
<BR>>users.<BR>><BR>>Regards,<BR>>Kev.<BR>><BR>><BR>>=
;--<BR>>National=20
Semiconductor, Tel: (408) 721 3251<BR>>2900 Semiconductor Drive, Mail =
Stop=20
D3-500, Santa Clara, CA 95052-8090<BR></FONT></BODY></HTML>
This archive was generated by hypermail 2b28 : Mon Mar 10 2003 - 10:28:18 PST