Subject: [sv-ec] 2 constraint issues
From: Jay Lawrence (lawrence@cadence.com)
Date: Mon Mar 10 2003 - 10:59:32 PST
The following are some brief issues with Chapter 20. My apologies for
not getting them in last week. I was travelling with almost no access
(Germany needs a new phone system).
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rand and randc as declarations instead of constraints
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I don't see why 'rand' and 'randc' are a part of the class declaration
and not just a form of constraint on these class members. I would think
that the user would declare a basic class with all members of the class
and no constraints or random indications, and then be able to inherit
this class into muliple testbenches which specify which variables are
random and how they are constrained.
Having them always procedural instead of declarative may eliminate the
need for $rand_mode at all.
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Bidirectional nature of implication
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The bi-directional nature of "implication" is very misleading. The term
implication is not bi-directional (the inverse is "inference"). Both the
operator and the name imply a uni-directional operation. I'ld like a
clearer way to specify this.
Why isn't the equivalent boolean representation sufficient?
===================================
Jay Lawrence
Architect - Functional Verification
Cadence Design Systems, Inc.
(978) 262-6294
lawrence@cadence.com
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