Fw: [sv-ec] Draft 4 LRM Issues


Subject: Fw: [sv-ec] Draft 4 LRM Issues
From: David W. Smith (David.Smith@synopsys.com)
Date: Tue Apr 08 2003 - 16:28:43 PDT


Here is Jonathan's issue in greater detail.

Any response or correction?

Regards
David

----- Original Message -----
From: Jonathan Bradford;Freiburg
To: David W. Smith
Sent: Tuesday, April 08, 2003 12:23 AM
Subject: Re: [sv-ec] Draft 4 LRM Issues

  
Hello David
my issue "4) 4.2 Packed an Unpacked Arrays p29" was that a description in the text seemed to be all wrong,
in the second paragraph on page 29 there is a sentence that reads :-

  Note: System Verilog accepts a single number (not a range) to specify the size of an unpacked arrays, like C. System Verilog should accept this type of declaration as a shorthand notation, this is [size] becomes the same as [size-1:0]. For example ...
I have nothing against the concept of using a shorthand [size] to imply [size-1:0], unfortunately that does not seem to be what the first sentence in paragraph 2 of page 29 is saying. It seems to be saying that only a single number, not a range, can be used to describe the size of a dimension (like C).
Surely not ?
Hope this clears up the intent of my message.

   Regards

       Jonathan
  

"David W. Smith" wrote:

  Hello Jonathan,Thanks for the review. We went through them today in committee and resolved all of the issues that you raised. I will be updating the web site and will send you a respond on the resolutions. The only item that there was some confusion on was with the following: 4) 4.2 Packed and unpacked arrays p29
     Note: unpacked array size, a range[n:m] or a singular size [p] as range shorthand ([p-1:0]) can be used to specify
     dimension - the text does not say this - it says no range and singular size only.We were not quite sure what the issue was that you were raising. Can you restate it please?RegardsDavidDavid W. Smith
  Synopsys Scientist

  Synopsys, Inc.
  Synopsys Technology Park
  2025 NW Cornelius Pass Road
  Hillsboro, OR 97124

  Voice: 503.547.6467
  Main: 503.547.6000
  FAX: 503.547.6906
  Email: david.smith@synopsys.com
  http://www.synopsys.com

    -----Original Message-----
    From: bradford@Synopsys.COM [mailto:bradford@Synopsys.COM] On Behalf Of Jonathan Bradford;Freiburg
    Sent: Monday, April 07, 2003 2:28 AM
    To: David W. Smith
    Subject: Re: [sv-ec] Draft 4 LRM Issues

    Hello David,

    as a System Verilog observer, here are some corrections for Draft 4 (upto section 10)
      

    1) 3.7 Chandle, p11

       define/clarify why chandle cannot be used in structures or unions
      

    2) 3.8.9 atoi() & 3.8.11 itoa() p15

        allow atoint() as alias for atoi() [ to complement atohex(), atooct() & atobin() ]
      

    3) 3.9 Event data type p16

       in description, clarify if event data type can be passed through port
      

    4) 4.2 Packed and unpacked arrays p29

       Note: unpacked array size, a range[n:m] or a singular size [p] as range shorthand ([p-1:0]) can be used to specify
       dimension - the text does not say this - it says no range and singular size only.
      

    5) 4.7 Array assignment p33

       p = {d[1:3],"hello", d[4:5]};

       This is the basis of list and queue manipulation. Good. Can it be extended to show pop ?

       p = d[1:4]

       Clarify that the dynamic array can be through an interface port.

       Can there be queues of queues ?

       How in above case can p be set to "a", "b", "c", "hello", "de"

       i.e. p = {d[1:3], "hello", (d[4:5]) }; ?

       as there may be an ambiguity in arrays of arrays and what is extending what slices & elements ?
      

    6) 4.8 Arrays as arguments p34

       ... passed arguments of compatible type and size ...

       Compatible type does not mean identical type - i.e. assignment compatible.

       Hence fun(int a [3:1][3:1]);

                  actual reg b [3:1][3:1]; should work as the copied values from reg to int are assignement compatible (x to 0 etc) ?
      

    7) 4.10.1 num() p37

       int imem[*];

       $display (map.num);

            imem or map variable ?
      

    8) 7.5 Wild equality and wild inequality p52

       operator !=== is a mistake surely, mean !== ?
      

    also <= non-blocking assignemt operator missing from precedence table.
      

    9) 9.6 fork join p71

       function int wait_20; contains timing ! (// illegal note just talks about fork/join & return)
      

    10) 10.2 Tasks p76

       formal arguments input, output, inout
       add ref as a 4th style - reference 10.5.2 later

       Do for functions too.
      
      

    Hope this is of use to you

          Jonathan Bradford
      
      
      

    "David W. Smith" wrote:

      Greetings,Just a reminder that I will be collecting ALL of the changes to Draft 4. Please make sure that you email me your changes once you have decided on them. I will then collected, organize, and submit them to Stu for inclusion in Draft 5. There will be a website with all of the changes once I start getting them in.RegardsDavidDavid W. Smith
      Synopsys ScientistSynopsys, Inc.
      Synopsys Technology Park
      2025 NW Cornelius Pass Road
      Hillsboro, OR 97124
      Voice: 503.547.6467
      Main: 503.547.6000
      FAX: 503.547.6906
      Email: david.smith@synopsys.com
      http://www.synopsys.com

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/\ Jonathan Bradford mailto:bradford@micronas.com \/ /\/\ MICRONAS GmbH http://www.micronas.com /\/\/\ \/\/\/ Hans-Bunte-Str.19 Tel: +49 (0)761 517 2884 \/\/ D-79108 Freiburg Fax: +49 (0)761 517 2880 \/ Germany



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