Re: Fw: [sv-ec] Draft 4 LRM Issues


Subject: Re: Fw: [sv-ec] Draft 4 LRM Issues
From: Stefen Boyd (stefen@boyd.com)
Date: Wed Apr 09 2003 - 12:16:57 PDT


At 04:28 PM 4/8/2003 -0700, David W. Smith wrote:
>Here is Jonathan's issue in greater detail.
>
>Any response or correction?

He has a good point. I would suggest the change:

REPLACE:

SystemVerilog accepts a single number (not a range) to specify the size of
an unpacked arrays,

WITH:

SystemVerilog also accepts a single number instead of a range to specify
the size of an unpacked array,



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