Subject: RE: [sv-ec] Handling of escaped identifiers.
From: Michael McNamara (mac@verisity.com)
Date: Fri Apr 11 2003 - 08:40:16 PDT
These questions are best directed to etf@boyd.com, the email address
for the Errat Task Force of the IEEE 1364 Working Group, where
extensive work is underway on improving the IEEE 1364 Verilog
Standard.
The Accellera effort to which you posted your email is looking at
future technologies and syntax for consideration of inclusion; whereas
the IEEE 1364 is working on the standard in use today.
I have forwarded your email to the right place.
-Michael McNamara
Chair, IEEE 1364 Verilog Hardware Description Language Working Group.
Raghuraman R writes:
> Hi,
>
> We are facing issues because the Verilog standard is not clear on the
> handling of escaped identifiers and the eda tool vendors are having
> different interpretations.
>
> Particular problem is that while the VPI call fetches the signal name
> prefixed with the escaped identifer, while dumping the VCD for example,
> the signal name is not printed with the escape character.
>
> I had already raised this issue and the response was that the standard
> is not clear enough. I would like to know whether there is any move to
> clarify the standard's position on the escaped identifier.
>
> Thanks.
> --
> Regds,
>
> Raghuraman R
> ASIC
> Texas Instruments (India) Ltd.
> Phone : +91-80-5099113
> http://www.india.ti.com/~raghu
>
> * Think. *
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