Subject: Re: [sv-ec] foreach loop
From: Arturo Salz (Arturo.Salz@synopsys.com)
Date: Mon Oct 13 2003 - 10:46:43 PDT
Ray,
My comments in blue.
Arturo
----- Original Message -----
From: "Ryan, Ray" <Ray_Ryan@mentorg.com>
To: "'sv-ec@server.eda.org'" <sv-ec@eda.org>
Sent: Monday, October 13, 2003 10:27 AM
Subject: [sv-ec] foreach loop
Regarding the foreach example in ext-15.
// 1 2 3 3 4 1 2 -> dimension numbers
int A [2][3][4]; bit [3:0][2:1] B [5:1][4]
foreach( B [ q,r,,s] )...
.... The second foreach causes q to interate from 5 to 1,
r from 0 to 3, and s from 2 to 1 (iteration over the 3rd index
is skipped).
Since the [4] in the declaration of B is equavalent to [3:0] shouldn't
'r' iterate from 3 to 0.
The declaration [4] is equivalent to [0:3]. That statement was an error
that is addressed by ERR-2. The proposal uses the "corrected" definitioin.
In an iterative constraint (ext-14), the iteration order is not
significant, however, in the more general construct (ext-15), the order
is signficant.
Yes. That is correct.
Also since the order is significant:
A foreach with multiple loop variables implies a nesting of loops, one
for each variable. The foreach definition (8.5.3) should specify the nesting
order of the loop variables.
Yes. Good point. I thought the nesting order was defined, but when I re-read
the proposal I realized that it is only implicit.
Ray
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