RE: [sv-ec] Action Item 25

Subject: RE: [sv-ec] Action Item 25
From: Jonathan Bromley (jonathan.bromley@doulos.com)
Date: Thu Oct 23 2003 - 01:22:48 PDT

> -----Original Message-----
> From: Arturo Salz [mailto:Arturo.Salz@synopsys.com]
> Sent: 22 October 2003 22:43
> To: Michael.Burns@motorola.com; david.smith@synopsys.com
> Cc: sv-ec@eda.org
> Subject: Re: [sv-ec] Action Item 25
>
>
> Mike,
>
> You are correct. Currently, SystemVerilog requires a default for a
> parameter.
> However, it does not need to be bit, it could be any other type
> Nevertheless, I can think of an enhacement to not require a
> default type [for the parameter]

It seems to me that this enhancement would be very valuable.
It would allow the creation of what you might describe as an
"abstract container class" that cannot be instantiated without
specifying its type parameter. 

-- 
Jonathan Bromley, Consultant

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