Subject: RE: [sv-ec] Action Item 25
From: Michael McNamara (mac@verisity.com)
Date: Fri Oct 24 2003 - 13:18:29 PDT
Is changing SV to allow untyped parameters an enhancement, or the
removal of a proposed change?
It is the case that IEEE Verilog allows untyped parameters already,
and they act just as Jonathan assumes:
module x;
parameter a = 755;
initial $display("%m: a is ",a);
endmodule
module y;
x x0();
x #(3.1415926) x1 ();
initial $display("%m: x1.a ",x1.a);
endmodule
module z;
x x0();
x #(32'h12345678) x1 ();
initial $display("%m: x1.a ",x1.a);
endmodule
Results in:
y.x0: a is 755
y.x1: a is 3.1415926
y: x1.a 3.1415926
z.x0: a is 755
z.x1: a is 305419896
z: x1.a 305419896
-- On Oct 23 2003 at 09:22, Jonathan Bromley sent a message:
> To: Arturo.Salz@synopsys.com, sv-ec@eda.org
> Subject: "RE: [sv-ec] Action Item 25"
> > -----Original Message-----
> > From: Arturo Salz [mailto:Arturo.Salz@synopsys.com]
> > Sent: 22 October 2003 22:43
> > To: Michael.Burns@motorola.com; david.smith@synopsys.com
> > Cc: sv-ec@eda.org
> > Subject: Re: [sv-ec] Action Item 25
> >
> >
> > Mike,
> >
> > You are correct. Currently, SystemVerilog requires a default for a
> > parameter.
> > However, it does not need to be bit, it could be any other type
> > Nevertheless, I can think of an enhacement to not require a
> > default type [for the parameter]
>
> It seems to me that this enhancement would be very valuable.
> It would allow the creation of what you might describe as an
> "abstract container class" that cannot be instantiated without
> specifying its type parameter.
> --
> Jonathan Bromley, Consultant
>
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