Subject: Re: [sv-ec] Err-5
From: Adam Krolnik (krolnik@lsil.com)
Date: Fri Nov 21 2003 - 10:03:55 PST
Hi Jay;
You wrote:
>In general we should just remove all reference to
>built-in and define these classes, types etc in the std package.
And add the following.
No additional elements shall be defined in the std package, except
those define by the <SystemVerilog> standard.
The last thing one needs is a loose definition of "standard" components.
Look at "C" for further justifications.
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
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