Subject: RE: [sv-ec] Err-5
From: David W. Smith (david.smith@synopsys.com)
Date: Fri Nov 21 2003 - 10:42:05 PST
Agreed. That is part of the original proposal.
Regards
David
-----Original Message-----
From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of Adam
Krolnik
Sent: Friday, November 21, 2003 10:04 AM
To: Jay Lawrence
Cc: sv-ec@server.eda.org
Subject: Re: [sv-ec] Err-5
Hi Jay;
You wrote:
>In general we should just remove all reference to
>built-in and define these classes, types etc in the std package.
And add the following.
No additional elements shall be defined in the std package, except those
define by the <SystemVerilog> standard.
The last thing one needs is a loose definition of "standard" components.
Look at "C" for further justifications.
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
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