======================================================================
http://www.eda.org/svdb/bug_view_page.php?bug_id=0000007
======================================================================
Reported By: dwsmith
Assigned To: salz
======================================================================
Project: SystemVerilog Errata
Bug ID: 7
Category: SV-EC
Reproducibility: always
Severity: feature
Priority: immediate
Status: assigned
Type: Errata
======================================================================
Date Submitted: 06-02-2004 14:26 BST
Last Modified: 08-31-2004 10:13 BST
======================================================================
Summary: Generate erratum on 1, 3, and 6 response to Ray's email
Description:
http://www.eda.org/sv-ec/hm/1826.html
======================================================================
----------------------------------------------------------------------
salz - 08-04-2004 15:02 BST
----------------------------------------------------------------------
Attached file proposes a new section 20.10, and clarification to section
20.4.1
Bug History
Date Modified Username Field Change
======================================================================
06-02-04 14:26 dwsmith New Bug
06-02-04 14:27 dwsmith Assigned To => salz
06-02-04 14:27 dwsmith Status new => assigned
06-03-04 15:36 sv-ec Bug Monitored: sv-ec
06-03-04 15:42 dwsmith Description Updated
08-04-04 15:00 salz File Added: svd-errata-6.pdf
08-04-04 15:02 salz Bugnote Added: 0000021
08-04-04 15:02 salz Resolution open => fixed
08-04-04 15:02 salz Status assigned => resolved
08-31-04 10:11 bpierce Resolution fixed => reopened
08-31-04 10:11 bpierce Status resolved => feedback
08-31-04 10:12 bpierce Status feedback => assigned
08-31-04 10:12 bpierce Type => Errata
08-31-04 10:13 bpierce Priority normal => immediate
======================================================================
Received on Tue Aug 31 10:13:06 2004
This archive was generated by hypermail 2.1.8 : Tue Aug 31 2004 - 10:13:08 PDT