[sv-ec] Jeda SV-EC errata: #13 masked bit operation

 
problem:
-------
The wild equality and inequality operators specified in SV 3.1a spec,
7.5 do not provide the ability to specify X's and Z's only on one side
of an expression evaluation(left or right hand side)

summary:
--------
Masked bit wise comparision operators that allow values of X's and Z's
for left and right hand side of an expression evaulation respectively.

description:
------------
These additional bitwise comparision constructs are proposed for
addition to the SV 3.1a specification as they've been found quite
important in Hardware Verification tasks. The operators perform a bit
for bit comparision of the left and right hand side values and return a
1-bit result. The operators functions are summarized as follows:

operator usage description
?== a ?== b a equals b, X and Z values allowed for
a
==? a ==? b a equals b, X and Z values allowed for
b

These operators are extensions of those specified in section "7.5 Wild
equality and wild inequality " of the SV 3.1a specification.

Typical application of these type of operators is when comparing results
from a dut vs. a model output. An expected result from a model can relax
checking by adding X's in its expected result value. in a case as
follows:

        logic [7:0] dutValue, modelValue;
        
        dutValue = 8'b1011_1010;
        modelValue = 8'bx011_1x10;

        if ( modelValue ?== dutValue )
           $display("Check worked\n");

Alternatively this can also be written as
        if ( dutValue ==? modelValue )
           $display("Check worked\n");
         

Additional information:
-----------------------

attached files:
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None

 
Received on Tue Aug 31 13:45:52 2004