[sv-ec] confirmation for use of 4 state values in constraints specifications

In p. 129 of the SystemVerilog LRM, it says "Constraints support only 2-sate
values. 4-state values (X or Z) or 4-state operators (e.g., ===, !==) are
illegal and shall result in an error."
 
Given this, can you confirm that
either:
  randomize( b ) with { b > 4'bxxxx };
 
or:
  c = 4'bxxxx;
  randomize( b ) with { b > c };
 
results in the generation of an error?
 
Francoise
       '
Received on Tue Oct 19 16:45:18 2004