Re: [sv-ec] confirmation for use of 4 state values in constraints specifications

Yes. Both your examples should result in an error.
In the first case, the compiler can issue the error.
In the second case, the run-time will issue the error.

Note that b > 4'bxxxx is not well defined.

    Arturo

----- Original Message -----
From: Francoise Martinolle
To: sv-ec@eda.org
Cc: 'Chiahon Chien'
Sent: Tuesday, October 19, 2004 4:45 PM
Subject: [sv-ec] confirmation for use of 4 state values in constraints specifications

In p. 129 of the SystemVerilog LRM, it says "Constraints support only 2-sate values. 4-state values (X or Z) or 4-state operators (e.g., ===, !==) are illegal and shall result in an error."

Given this, can you confirm that
either:
  randomize( b ) with { b > 4'bxxxx };

or:
  c = 4'bxxxx;
  randomize( b ) with { b > c };

results in the generation of an error?

Francoise
       '
Received on Tue Oct 19 18:01:27 2004