[sv-ec] enum issue

At the last meeting, Brad was supposed to ask the EC for input on
erratum 216. Unfortunately, there wasn't enough time. Given the
schedule constraints, the BC needs input so that they can proceed
on this issue.

The erratum points out that 4-state enums might be used for state
machine states, and therefore need to be initialized to X. This is
independent of how the enum values have been defined. The current
initialization rule in SystemVerilog will not correctly simulate
hardware initialization, and could result in production of faulty
hardware.

Brad was concerned that this might cause problems for something in
the testbench space, and wanted to consult the EC about it.

Steven Sharp
sharp@cadence.com
Received on Fri Oct 22 13:30:37 2004