[sv-ec] clocking blocks and `delay_mode_zero (or similar)

From: Gordon Vreugdenhil <gordonv_at_.....>
Date: Wed Dec 05 2007 - 15:02:23 PST
`delay_mode_zero (and related) are non-normative definitions
in the LRM but are widely supported.  Does anyone have opinions
on whether input and output skews for clocking blocks should
be impacted by delay modes?  In particular, should clocking
block drives to wires be considered to be more "structural"
or "behavioral" in nature?

My (very weak) opinion is that for regs, the delays should
almost certainly be "behavioral" and thus not be impacted
by delay mode specification.  For nets, I have no opinion
at this point since it isn't clear to me whether non-zero
output skews to nets are normally being used to model structural
net delays (and therefore probably should be impacted) or
whether there are other factors in play.

So, particularly from the users, any opinions on what you
would expect?

Gord.
-- 
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Gordon Vreugdenhil                                503-685-0808
Model Technology (Mentor Graphics)                gordonv@model.com


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Received on Wed Dec 5 15:02:44 2007

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