Re: [sv-ec] clocking blocks and `delay_mode_zero (or similar)

Hi Gord,

One thing that I just noticed is that the description of these
compiler directives only mentions modules. It doesn't say
anything about program blocks. My biggest concern is
with clocking blocks contained within program blocks. For
clocking blocks contained within programs I would not expect
`delay_mode_zero to have any effect on clocking block input and
output skews. In particular, it wouldn't make sense to change
the definiton of a #1step nor #0 clocking block delay.

When clocking blocks are used in modules it just might make sense
to honor these compiler directives.


Neil



Gordon Vreugdenhil wrote:
> 
> `delay_mode_zero (and related) are non-normative definitions
> in the LRM but are widely supported.  Does anyone have opinions
> on whether input and output skews for clocking blocks should
> be impacted by delay modes?  In particular, should clocking
> block drives to wires be considered to be more "structural"
> or "behavioral" in nature?
> 
> My (very weak) opinion is that for regs, the delays should
> almost certainly be "behavioral" and thus not be impacted
> by delay mode specification.  For nets, I have no opinion
> at this point since it isn't clear to me whether non-zero
> output skews to nets are normally being used to model structural
> net delays (and therefore probably should be impacted) or
> whether there are other factors in play.
> 
> So, particularly from the users, any opinions on what you
> would expect?
> 
> Gord.




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