[sv-ec] Assertions & Covers in classes?

Hi, All -

An interesting topic came up this week in a verification training class.

Has any consideration been give to adding assertions and cover
statements to classes?

The assertions and covers could be quite useful in a scoreboard
setting since the statements have rather powerful temporal
speicfication capabilities. One would still need to access signals
via a virtual interface, but it could be quite useful.

Regards - Cliff

----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
14355 SW Allen Blvd., Suite #100, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
cliffc@sunburst-design.com / www.sunburst-design.com
World Class Verilog & SystemVerilog Training

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