[sv-ec] Re: [sv-ac] Assertions & Covers in classes?

Cliff,
  We have been hearing this from local customer for well over 4 years.
During SV-2011 requirement gathering I had brought this up and we have
a brief Mantis too: http://www.eda.org/mantis/view.php?id=3031 But we
need "push".

I agree there are technical challenges, and this could be simulation
only feature as well. But there are some real needs from real users
and we would serve them better if we add this. However I believe SV-AC
has enough prioritized set of things from various parties and this
"feature" is not on the top-priority list as far as I understand.

BTW, from your original email:

> The assertions and covers could be quite useful in a scoreboard setting
> since the statements have rather powerful temporal speicfication
> capabilities. One would still need to access signals via a virtual
> interface, but it could be quite useful.

  If your asserts & covers are going to be about signals from virtual
interface, it is rather recommended to add them inside interface
itself. Also in a good methodology (OVM/UVM/VMM) the scoreboard should
not access the virtual interface in general, rather it is a higher
level abstracted checks/scores. The lower level, detailed
timing/protocol checks are dealt at so called "operational domain" or
at interface level itself.

Regards
Srini
www.cvcblr.com

On Sat, Nov 6, 2010 at 3:18 AM, Clifford E. Cummings
<cliffc@sunburst-design.com> wrote:
> Hi, All -
>
> An interesting topic came up this week in a verification training class.
>
> Has any consideration been give to adding assertions and cover statements to
> classes?
>
> The assertions and covers could be quite useful in a scoreboard setting
> since the statements have rather powerful temporal speicfication
> capabilities. One would still need to access signals via a virtual
> interface, but it could be quite useful.
>
> Regards - Cliff
>
> ----------------------------------------------------
> Cliff Cummings - Sunburst Design, Inc.
> 14355 SW Allen Blvd., Suite #100, Beaverton, OR 97005
> Phone: 503-641-8446 / FAX: 503-641-8486
> cliffc@sunburst-design.com / www.sunburst-design.com
> World Class Verilog & SystemVerilog Training
> --
> This message has been scanned for viruses and
> dangerous content by MailScanner, and is
> believed to be clean.

-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.