Re: [sv-ec] assignment pattern as LHS

i've reported mantis on this feature
http://www.verilog.org/mantis/view.php?id=3296

DANiel

On 11/2/2010 2:08 PM, Daniel Mlynek wrote:
> LRM says:
> "When an assignment pattern is used as the left-hand side of an
> assignment-like context, the positional notation shall be required;
> and each member expression shall have a bit-stream data type that is
> assignment compatible with and has the same number of bits as the data
> type of the corresponding element on the righthand side."
>
> As far as I understand this statement array of non bit stream types
> (real, handles event, chandles) cannot assigned to assignment pattern ie:
> real re[2], re1,re2;
> initial '{re1, re2} = re;
>
> Similarly when bit length of elements of LHS assignment pattern and
> RHS array elements do not match - then assignment also should trigger
> an error:
> int iarr[2];
> byte b1,b2;
> initial '{b1, b2} = iarr;
>
> If I'm right then I have 2 questions:
> - should those rules be really so strict ? maybe it can be relaxed
> - rules for unpacked struct assignment pattern used on LHS are same as
> for arrays? only bit stream data types
>
>
> DANiel
>
>

-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.