RE: [sv-ec] input skew

From: Bresticker, Shalom <shalom.bresticker@intel.com>
Date: Wed Jun 22 2011 - 01:14:44 PDT

Wouldn't #1 mean 1 time unit as specified by the timescale?

Shalom

From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of Daniel Mlynek
Sent: Wednesday, June 22, 2011 9:53 AM
To: sv-ec@eda.org
Subject: [sv-ec] input skew

LRM senstences:

1. A 1step input skew allows input signals to sample their steady-state values in the time step immediately before the clock event (i.e., in the preceding Postponed region).

2.If the input skew is not an explicit #0, then the value sampled corresponds to the signal value at the Postponed region of the time step skew time units prior to the clocking event

sugest that #1step and #1 input skew are the same

So is clocking event occurs in time 10.
Then sampled value is taken from postponed region of time 9 in both cases
Is it how it should work If so then 1step is redunand.

DANiel

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Received on Wed Jun 22 01:15:18 2011

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