Subject: Verilog++ Meeting Minutes Jul30th, 2001
From: David Kelf (davek@co-design.com)
Date: Mon Jul 30 2001 - 15:30:03 PDT
Hi Everyone,
Please find attached the minutes of the last Verilog++ Meeting.
Dave
Verilog++ 4th committee meeting
July 30th, 2001
Attendees:
(aaaa) Vassilios Gerousis *
(aaaa) Dave Kelf *
(aaaa) John Sanguinetti *
(aaa-) John Emmitt
(a---) Dennis Brophy
(aaaa) Stu Sutherland *
(aaaa) David Knapp *
(-aaa) Tom Fitzpatrick *
(aaa-) Phil Moorby
(aaaa) Anders Nordstrom *
(aaaa) Cliff Cummings *
(aaaa) Simon Davidmann *
(aa--) Harry Foster
(-aaa) Stefen Boyd *
(aaaa) David Smith *
(-aa-) Mike McNamara
Attendance record key
a = attended, r = representative sent, - = not present
* beside name means attended this meeting - to make it more obvious
Logistical Discussion:
- Stu's contract still being resolved with Accellera Administration
- Simon will send ESS docs to Stu, to provide basis of work
- Replies to reflector need to go back to reflector - please ensure
vlog-pp@eda.org is included on all correspondence.
- Kelf needs to follow up with open issues with Peter F, etc., on a couple
of previous questions, from the last meeting.
- Web site still being worked on.
- Process for email questions. Try to resolve by email correspondence. If
this is not possible they can be brought up at next meeting.
Email questions from the previous two weeks
DavidS
1. Out of range read and writes email question - needs clarification on
result - Simon said that we will need to write something up as it can be
complex.
Action - Dave To Get Simon to write this up.
2. Time precision - need to clarify what happens on rounding.
Action - Dave To get clarification.
Review of ESS Manual - Pages 21-31
Page 21 - Anders: Assignment can be an expression - does this cause syntax
issues for Verilog
Clarification on the use of = operator in expressions required, precedence,
are assignments right associative.
Note brackets are required.
David S - assignment operator is very distinct from assignment expression -
needs statement
Action - clarification of wording - DaveK
Page 21 - Anders: bump operators. How do we size the '1'. For example what
happens to the 1 the case of overflow. Statement needed in doc on the
"size" of the 1. Suggested wording: The resultant size of the operator is
the size of the operand.
Action - Stu to include wording in doc.
Page 21 - Anders: && and || are a bit confusing. Clarification required on
affect. Compare with current reduction operators.
Action - Dave to get clarification.
Page21 - Stu: Comma operator dropped? Simon explained. Fine as is. No action
Page 23 - Anders: B is evaluated if returns X? Requires evaluation? Cliff
explained that there situations where this is required. No action.
Page 22 - Dave Knapp: BNF maybe wrong - bump operator followed by primary
omitted. Maybe change ++ | -- in unary to <bump_operator> - clearer. Needs
looking at.
Action Dave to discuss with Peter.
Page 24 Dave S: Concats used to initialize arrays. Possible alignment
problems, especially when packing is included. Is there a difference
between contacts and initialization. Needs clarification - shows bit image
for example
Action: Dave to get from Peter
Page 25 and beyond - Cliff: BNF global change remove _ in
non_blocking_assignment and - in non-blocking (page 26) as per V2K docs
Action: Stu: will implement
Page 25 Cliff: Clarification in docs Break and Continue do not require names.
Action Stu to implement.
Page 25 - Cliff: more description on written required.
Action Dave to get clarification from Peter.
Page 26 - Following assignments allowed in Verilog - first 3 (with ns) not
allowed in Verilog - should describe more fully. Add ns examples for
Superlog only.
Action: Stu to implement.
Page 26 Cliff - Statement at end of page on synthesis should be removed.
Action Stu to implement.
Page 27 - Anders - what happens if there is a conflict between full and
parallel, and unique and priority - if they are both put in. Discussed tool
issue versus language issue. Note full, parallel added shown as example
attributes in V2K1.
Action: DaveK - get clarification from Peter
Action: Cliff to propose new wording.
Page 27 Cliff - almost needs a warning comment on full and parallel.
Action Cliff : Possible new wording proposal., as above.
Page 29 Anders - label before end. Clarify. Is this different.
Action: DaveK to get clarification from Peter.
Page 29 Cliff: Another example required label:begin .... end: label
Action: Stu to implement.
Page 29 Vassilios - Is there a goto - needs explanation. General opinion -
Should be dropped
Action: DaveK to get clarification from Peter.
Page 28 BNF does not match 75
Action: DaveS to write email.
Action Stu to implement.
Page 29 Cliff - what happens of you disable a non-blocking assignment with
a delay on right hand side. We should define a behavior for disable in
non-blocking assignment with delay on right hand side. Would be nice at
this point to define this - open to reasonable description. John - suggests
we need a mechanism for reset. This could be it.
Action Cliff will show example disable usage for reset, and try it on
different simulators, with Stu's help.
Page 29 Tom - document should describe what happens to non-blocking
assignment with disable as well as break and continue.
Action: Cliff will include break and continue in examples.
Page 30 Cliff - Transitions (posedge,negedge) need more clarification for
logic and not logic types.
Action - DaveK to get clarification from Peter.
Page 30 and elsewhere - net should be included in other @ descriptions as
well as variable, as it is on bottom of this page.
Action: Stu to implement.
Page 31 Cliff - wait expression slightly incorrect - posedge can go to X
as well as 1. Remove the "so it is equiv" sentence
Action: Stu to implement.
Next meeting:
August 13th 12:2 EDT
Call In 405 244 5555 access code 3715
Agenda review:
Pages 32 - 50
State Machines (including transition from above)
Processes
Tasks and Functions
Gates and UDPs
Hierarchy
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