Vlog-pp - Verilog++
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Starting: Mon Jul 16 2001 - 12:18:56 PDT
Ending: Mon Jul 22 2002 - 09:20:04 PDT
- "universal" logic type
- $assert* bnf
- $root proposal
- $root, prototypes etc.
- (no subject)
- .*
- .* and .name Implicit Port Declaration Proposal - 20020317
- .* and .name proposals - Cliff votes yes
- .name / .* and interface section proposals
- .name/.* voting
- 24th Verilog++ Meeting Minutes 4/22/02
- 25th Verilog++ Meeting Minutes 4/29/02
- 26th Verilog++ Meeting Minutes 5/6/02
- 27th Verilog++ Committee Meeting Minutes 5/20/02
- Accellera Board's Review of Technical Committee Rules
- Accellera Open Membership Meeting at DAC
- Accellera TCC Donation Process
- Accellera Voting : Delay FSM to 3.1
- Actions from 19th Committee Meeting 3/18/02
- Actions from BNF review on March 14
- Addendum to section 4.2: signed packed arrays
- Adding Regular Expressions to Instantiation?
- addition for intro of systemverilog3.0 document
- Additional Issues List
- additional minutes
- Adjustment to DRAFT 4
- Agenda for May 20 Meeting
- AMS Data & Simulation Model Update
- An Open Process
- An Update
- Annex B Replacement Proposal
- Another Sunburst Design FSM Example Design
- ANSI-Parameter List Bug and Ambiguities
- Array proposal for SystemVerilog
- arrays in SystemVerilog
- Assertions spec available for review
- Assign-Deassign Notes & Two iff typos in Draft 5
- Assignment statement versus assignment operator
- Attendance Record Discrepancy
- Begin-End / { } / < > ?
- BNF comments to discuss tomorrow
- BNF for jump
- BNF question
- BNF Questions? - FrameMaker BNF Should be the golden BNF file
- bnf update - PLEASE REVIEW
- Both Deprecation Proposals Pass E-Mail Vote
- bump operators. How do we size the '1'
- C/C++ subcommittee
- cannot dial in - "conference has ended"
- cannot dial in - keep trying
- Chairman for Enhancement Committee
- Changed the front pages of SystemVerilog 3.0 LRM
- Clarification to section 3.5 - user-defined types.
- Clarification to section 3.5 - user-defined types.]
- Clean up items to sections 8 and 10
- Cliff Cummings - FSM Proposals and models
- Cliffc Review Notes
- comments on array proposal
- Comments on packed arrays
- Committee Attendance List
- Conference Call Died?
- Conference Call this morning
- Correction: January 7, 2002 Verilog++ Committee Meeting - Reminde r
- DAS Donation From Co-Design
- datapath enhancements to verilog
- datapath enhancements to verilog, extern etc.
- December 7, Verilog++ Committee Meeting - Reminder
- DeCSS Verilog Source WITH FSM -- Convert to SystemVerilog ?
- Deprecate Proposal #2
- Deprecating assign/deassign - response to Kevin's comments
- Deprecation Proposal
- Deprecation Proposals - Official Final Vote
- Donation Materials
- Draft 5 attached
- Draft 5 status
- Draft 7 - Typos - Enumeration examples page 8
- Dynamic Process naming/control
- editorial comments on draft 8
- Editorial Notes SysteVerilog 3.0/draft 9
- editorial suggestion regarding "integer"
- EEDesign Poll
- enum literals
- Enumerated Types Proposals
- Enumerated Types Proposals - Responding to Kevin and Peter
- Enumerated Types Proposals - Responding to Stu's comments
- Enumeration Proposals
- errata section 8.3
- examples of root for systemVerilog
- External Module Definitions
- External module definitions proposal
- External Modules/$root
- Face to Face Meeting On November 12 at Mentor Graphics -- San Jos e
- Face to Face Meeting On November 12 at Mentor Graphics -- San Jose
- Face To Face Meeting on Wednesday June 5, 2002
- Final Reminder For Joining SV committees
- Final SystemVerilog 3.0 LRM
- FSM Enhancement Goals and Thoughts
- FSM Section Vote
- FSM Section Vote Results
- FSM Section Vote?
- Further issues (mostly for SV-BC)
- Fwd: Actions from 10th Meeting Verilog ACE Oct 22nd 2001
- Fwd: datapath enhancements to verilog
- Fwd: minutes of Accellera HDL+ committee meeting on systemve rilog 3.1 5th June 2002 at snps
- Fwd: minutes of Accellera HDL+ committee meeting on systemverilog 3.1 5th June 2002 at snps
- Fwd: Minutes Verilog++ Meeting July 16th
- Fwd: Moving Ahead on SystemVerilog 3.1 Despite Politics
- Fwd: SystemVerilog draft 6
- globals and name searching
- Handling of "implicit" declarations
- Handling of variables on port declaration and usage
- HDL+ June 2002 Minutes - Modified
- HDL+ Meeting -- March 14 meeting at Mentor Graphics
- HDL+ SystemVerilog 3.1 Planning Meeting Minutes and Presentat ions
- HDL+ SystemVerilog 3.1 Planning Meeting Minutes and Presentations
- Hierarchical FSMs?
- Implicit register variables and .* instantiation?
- Information for meeting on 8 July 2002
- Integer types in BNF
- Intel/Synopsys pushing Assertion Language
- Interface Chapter Introduction Proposal
- Interface Section Modification Proposals - 20011217
- Invitation to Accellera's Annual DAC Breakfast & Panel
- issues for next telcon
- Issues List - Additional Details
- Jeda Language
- Jumpered ports
- June 5 HDL+ Committee Meeting At Synopsys Building B Mountain Vie w
- June 5 HDL+ Committee Meeting At Synopsys Building B Mountain View
- June 5th Meeting for HDL+ committee meeting -- PLEASE RSVP.
- Keyword Caution (was: keyword 'cell')
- List of 3.1 Items
- Localparam documentation bug??
- Meeting Reminder Monday 5th
- Meeting Today
- Minor clean up questions, sections 1 to 7
- Minutes 10th Meeting Verilog ACE Oct 22nd 2001
- minutes of Accellera HDL+ committee meeting on systemverilog 3.1 5th June 2002 at snps
- Minutes Verilog++ 7th committee meeting
- Minutes Verilog++ 8th committee meeting
- Minutes Verilog++ 9th Committee Meeting
- Mixed-signal nets, Interfaces & Abstract Types
- more on downloading Verilog++ LRM draft 1
- More Thoughts on Jeda
- Moving Ahead on SystemVerilog 3.1 Despite Politics
- Moving Ahead with SystemVerilog 3.1 Despite Politics.
- Names created by generate, array of gates and array of instances allow "[]" without escaping the name
- net structs?
- New Dates and New Plans - IMPORTANT
- NEW FSM Syntax Proposals and Examples -20020325
- New Sucker (member) of the SystemVerilog Standards Group
- Next Meeting Of The Verilog++ Group
- Notes from last weeks meeting
- Official Issue List for SystemVerilog 3.1 and comments
- Our meeting on February for February 18
- Our Next meeting November 26.
- Our Next teleconference call -- Reminder
- Parameter Interface Bugs?? Clarification?? Enhancement??
- Parameters Errata in Draft 5
- PASSED (SystemVerilog) - ANSI-Style Parameter Port List BNF Correction
- PASSED - Enumerations Proposal
- PASSED - Implicit Ports Proposals
- PDF copy of SystemVerilog 3.0 LRM
- Please Welcome David Lacey As The Assertion Committee Chairman
- Poll of the Week - www.eedesign.com
- Port connection in general
- Port Connection Rules
- pragmas
- problem with incomplete type references in draft 8
- Proposal for array types
- proposal pair for named port definitions
- Proposal to Delete the new SystemVerilog FSM syntax
- Proposal: Deprecate defparam
- Proposal: Deprecate procedural assign-deassign
- Proposal: Implicit Port Instantiation in SystemVerilog
- PROPOSAL: Remove the SystemVerilog State Machine Section
- PROPOSAL: Remove the SystemVerilog State Machine Section - Response to Anders
- propose limitation of $root declarations
- Proposed BNF Fix for Verilog-2001 Parameter Errata
- Protesting the IEEE-SA membership fee
- question about array port mismatches
- Question on draft 3, section 10.5
- Question on timeprecision
- Questions on section 11
- Questions on section 8.10
- Quotation marks in the SystemVerilog Standard.
- Reg-Removal Proposal Paper
- Reminder for August 27 Conference Call.
- Reminder for our meeting on Monday December 10a
- Reminder For reading SystemVerilog Document
- Reminder: LRM Committee Call
- Return to professionalism...
- Revised BNF
- Section 10.3 always_comb and function sensitivity
- September 10 Conference Call == Plans for Face to Face Meeting on September 24.
- Size of members of a packed union
- Slices
- Some Action Items To Formalize Our Discussions and voting for nex t meeting
- Some Action Items To Formalize Our Discussions and voting for next meeting
- Some Action Items To Formalize Our Discussions and voting for next t meeting
- Starting Up the SV-CC Committee
- State machine encoding (etc.)
- Suggestion for "implicit variables"
- summarry of $root proposals
- Support the HDL+ Chairs and Let us Start Working
- SV-Basic and SV-Enhancements Subcommittee Meetings Call Informat ion
- SV-Basic and SV-Enhancements Subcommittee Meetings Scheduled
- SV-BC Info & Conference Call Agenda
- SV-BC: Issues List - Additional Details
- SV-BC: Minutes from July 8, 2002 meeting
- SV-EC agenda for 28 June 2002 9:00-11:00 meeting
- SV-EC committee
- Synopsys Donates Key Verification Technologies to Accellera's SystemVerilog 3.1 Standard
- Synopsys sv3.1_donation_Assertion
- Synopsys sv3.1_donation_C-InterfaceAPI
- Synopsys sv3.1_donation_CoverageAPI
- Synopsys sv3.1_donation_VeraLite
- System Verilog 3.0 document
- System Verilog Draft 3 - Zip and protected
- SystemVerilog - Accellera -vs- IEEE
- SystemVerilog - FSM OneHot Enumerated Types - Display Problem
- SystemVerilog 18th Committee Meeting Minutes 14/3/02
- SystemVerilog 19th Committee Meeting 3/18/02
- SystemVerilog 20th Committee Meeting 3/25/02
- SystemVerilog 21st Meeting Minutes 4/1/02
- SystemVerilog 22nd Committee Meeting 4/8/02
- SystemVerilog 3.0 - Question about constant declarations
- SystemVerilog 3.0 draft 9
- SystemVerilog 3.0 is Officially An Accellera Standard
- SystemVerilog Attendance List
- SystemVerilog Draft 3
- SystemVerilog draft 4
- SystemVerilog draft 6
- SystemVerilog draft 6 - structs,unions & packing.
- SystemVerilog draft 7
- SystemVerilog draft4 - PRELIMINARY
- SystemVerilog Keywords
- SystemVerilog LRM and Accellera Board Voting - A Suggestion f or moving forward
- SystemVerilog LRM draft 8
- SystemVerilog Press Release
- SystemVerilog Press Release For DAC 2002
- SystemVerilog Typos
- SystemVerilog vote
- SystemVerilog Voting Rules - Correction
- SystemVerilog: always_comb and functions
- Teleconference Agenda
- Test - please ignore
- Test: [Fwd: Welcome to vlog-pp]
- Tested Interface Examples
- Thoughts about arrays in SystemVerilog
- Thoughts on the .* proposal
- Time To Act And Stop The Politics
- Today's call...
- today's meeting
- UDPs
- Unconnected inputs
- Unions - overlaying bits & logic
- Unsized array declarations using .name / .* and interfaces
- Updated Assertion document version 1.6
- updated bnf
- Updated HDL+ Document
- Updated Implicit Ports Proposal
- Updated Minutes for March 14th Meeting
- User defined types
- Using iff example
- Using iff example - very bad coding style!
- Verif Guild - Vol 3, no 09
- Verilog ++ committee on November 5 - Agenda And Discussion
- Verilog++ -- Assertion Committee Slides.
- Verilog++ 11th Committee Meeting Minutes
- Verilog++ 12th Committee Meeting Minutes (Face to Face)
- Verilog++ 13th Committee Meeting - 11/26/01
- Verilog++ 14th Committee Meeting Minutes
- Verilog++ 15th Committee Meeting 7 Jan 2002
- Verilog++ 16th Committee Meeting 28 Jan 2002
- Verilog++ 16th Committee Meeting 28 Jan 2002 - Attendance correction
- Verilog++ 5th committee meeting - minutes - August 13th, 2001
- Verilog++ 6th committee meeting
- Verilog++ Assertion Requirements Proposal
- Verilog++ LRM draft 1
- Verilog++ LRM draft 1 is ready
- Verilog++ LRM draft status
- Verilog++ Meeting Attendance
- Verilog++ Meeting Minutes Jul30th, 2001
- verilog++ meeting today - agenda
- Verilog++ Schedule - and Majordomo Test
- void keyword
- VOTE - Deprecating assign (use force)
- VOTE - Deprecating assign/deassign
- VOTE - Two Deprecation Proposals - Votes due Wed., April 17
- Vote on LRM
- Vote on Monday: (1) Implicit Ports (2) Deprecation (3) Enumerated types (4) BNF parameter fix
- Voting for SystemVerilog
- Voting on implicit connections
- Voting Results as of 5/30 by the Accellera Board
- Voting Results for SystemVerilog
- We are now ready to start working
- Welcome again And Our Next meetings
- Welcome to Jayan Nagda
- Welcome to the email reflector
- Welcome to the Verilog++ EMail Reflector
- your implicit port connection proposal
Last message date: Mon Jul 22 2002 - 09:20:04 PDT
Archived on: Mon Jul 22 2002 - 09:20:43 PDT
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: Mon Jul 22 2002 - 09:20:43 PDT