Subject: Verilog++ 15th Committee Meeting 7 Jan 2002
From: Stuart Sutherland (stuart@sutherland-hdl.com)
Date: Fri Jan 25 2002 - 23:09:31 PST
Verilog++ 15th Committee Meeting
January 7th, 2002
Vassilios leading. DaveK/Stu taking minutes
(aaaa-aaaaaaaaaa) Vassilios Gerousis *
(aaa-aaarar-aaaa) Dave Kelf
(-----aaa--aaaa=) John Sanguinetti
(aaaaaa--a-aa---) Dennis Brophy *
(aaaaaaaaaaaaaaa) Stu Sutherland *
(a--------aaaaa=) David Knapp *
(-aaaaaraaar-aaa) Tom Fitzpatrick
(-arraa-aaaaaaa=) Phil Moorby
(a-aaaa-aaaaaaaa) Anders Nordstrom *
(aaaa--a-aaaaaa=) Cliff Cummings *
(aaaaraaa-aaaaaa) Simon Davidmann *
(aaaaaaaaaaa====) Peter Flake *
(aaaa-aaaaa-aaaa) Stefen Boyd *
(aaaaaaaaaaaaaaa) David Smith *
(a-aaa--a-a--aa=) Mike McNamara *
(aaaaaaaa=======) Kevin Cameron *
(a-a-aa-a=======) Andy Tsay *
(-aa============) Alec Stanculescu
(-a=============) Adam Krolnik
(a==============)Paul Graham *
(a==============) David Seieert *
Paul Graham of Cadence is joining the group for the first time. Paul is
working on data path extensions to the Verilog HDL. Cadence hopes these
extensions will become part of a future Verilog standard. It appears there
is some overlap between Paul's work and SystemVerilog. More on this will
be discussed at a future meeting.
Question from Paul regarding array specifier syntax. Peter F answer based
on simulation efficiency. Synthesis use also discussed by Paul and David Knapp.
--------
Agenda item a: always_comb rules.
Stefen brought up always_comb and made a case for retaining this construct.
Need to allow for a static checking. Benefit is that provides more
information on usage and is more rigorous. Alternative is attribute for
pragmas. Stefen would like to make sure this is included. Generally agreed
that it is a good thing. Discussion around trapping errors in simulation
versus tools like synthesis. Resolution:
1) Add to section 10.3 of draft 3:
The SystemVerilog always_comb procedure differs from the Verilog always @*
in the following ways:
o always_comb automatically executes once at time zero,
whereas always @* waits until a change occurs on a signal
in the inferred sensitivity list
o always_comb is sensitive to changes within the contents of
a function, whereas always @* is only sensitive to changes
to the arguments of a function.
o variables on the left-hand side of assignments within an
always_comb procedure may not be written to by any other
processes, whereas always @* permits multiple processes to
write to the same variable.
2) Software tools may perform additional checks to warn if the behavior
within an always_comb procedure does not represent combinational logic,
e.g.: if a latched behavior may be inferred.
3) Strike the sentence in section 10.3, draft 3, that reads: "In the case
of the always_comb block, every variable..."
4) Separate always_comb and always_latch into separate sections, as shown
in the editor note in section 10.3, draft 3.
---------
Agenda Item b: What should happen for a mismatch on port connections.
Postponed discussion because Stefen had dropped off the call.
---------
Agenda Item c: State Machines.
Cliff feels there is very little added value in the SuperLog state and
transition concepts. Some enhancements to SystemVerilog enumerated types
are all that is really needed. Refer to Cliff's e-mails 12/11/2001 to
12/13/2001.
Peter F has not had time to look at Cliff's e-mails.
Cliff did not look at the traffic light exercise sent in by Alex S. Cliff
feels the example is contrived, and that there is no value in examples that
do not reflect real-life modeling issues.
Vassilios raised the concern that no one is addressing whether the Superlog
state and transition constructs add value to modeling FSMs at a higher
level of abstraction.
Cliff says his e-mails of 12/11/2001 did not address new abstraction
levels, but that at current RTL levels, enumerated types is all that is
needed. This style provides engineers a straightforward path to more
detailed hardware implementation. A more abstract level of modeling must
also provide a straight forward path to implementation.
Cliff clarified enhancements needed to enumerated types. The current
syntax does not support a one-hot style. Suggests adding a enum_onehot
construct
Stu proposed that the SuperLog state and transition constructs not be
included in the first version of SystemVerilog. It can be reviewed for a
future version. Vassilios said to wait on this decision until after the
value of these constructs are discussed further.
Action items:
- Cliff to contact Kurt Baty for real-life hierarchical FSM examples.
- Anders to show example where SuperLog state and transition made and RTL
FSM model more compact and readable.
- Peter F. to review Cliff's e-mails.
- Stu to create a draft 4 by 1/25/2002 that reflects resolutions from past
3 or 4 meetings.
---------
The remainder of the agenda items will be discussed at the next meeting.
The next meeting scheduled for Monday, Jan 28th.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Stuart Sutherland Sutherland HDL Inc.
stuart@sutherland-hdl.com 22805 SW 92nd Place
phone: 503-692-0898 Tualatin, OR 97062
www.sutherland-hdl.com
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