Subject: Handling of variables on port declaration and usage
From: David Smith (david_smith@avanticorp.com)
Date: Fri Aug 24 2001 - 15:44:39 PDT
I have not had any discussion on this yet. Anythoughts?
David
> -----Original Message-----
> From: David Smith
> Sent: Wednesday, August 22, 2001 3:26 PM
> To: 'vlog-pp@eda.org'
> Subject: Handling of variables on port declaration and usage
>
> Greetings,
> In my discussions with the Verilog-AMS committee there is a capability that they have added to the Verilog-AMS specification that I believe is support in Verilog++.
>
> Let me set the stage:
>
> Three modules are defined.
> module b is:
>
> module modB(inout real ba, inout real wbb, inout real wbc);
> ...
> endmodule
>
> module c is:
>
> module modC(inout real ca, inout real cb, inout real cc);
> ...
> endmodule
>
> module a is:
>
> module modA(inout real aa, inout ab)
> real a;
>
> modB m1 (a, ab, bb)
> modC m2 (b, aa, bb)
> ...
> endmodule
>
> The desire is to be able to have an implicit variable connection in addition to the implicit net connection. The m1 instance clearly obeys strong typing for the first argument since a and aa are both typed. The second argument of modB gets its data type from instance of modA (not defined and may be undeclared unless connected to another instance at the same level) and from modB. The third argument of the modB instance is implicit in its definition and comes from the declaration in modC and modB.
>
> My question here is whether the above is correct. Is an unnamed variable also an implicit variable that inherits type from the connections?
>
> This makes sense based on how Verilog handles implicit net types. It seems in direct contradiction to the definition of section 3.5 of the 2001 specification. I cannot find it specified in the SuperLog document. For netlisting purposes and "configuration" support it makes sense for a variable to able to be implicit as well as a net.
>
> Thoughts?
>
> David
>
> David W. Smith
> Architect
>
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