Subject: Re: Handling of "implicit" declarations
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Tue Sep 25 2001 - 12:17:20 PDT
> What is a wire? The Verilog-AMS mechanism for wreal should not be required when using Verilog++ since reals are well behaved.
>
One of those things made out of metal (or polysilicon) that carries electrons
from one place to another :-)
Actually, more generally something that would end up as a 'node' in circuit
analysis.
> What is a physical type? Not defined in the language.
I meant 'physical' in the sense that it is bound to a physical object as far
as hardware description is concerned (i.e. a wire, as above).
> Maybe the concept of wire is good but what about busses (they are physical too from the point of view of place and route)? They do not behave well when a wreal is connected to a reg (Verilog rules say to take the least significant bit only on implicit connections).
A bus is constructed from wires, hence my point about knowing the difference between an
integer representing 32 wires or 1. - maybe the former would be type 'integer' and the
latter 'winteger'.
'wreal' is (I presume) meant to be a single wire carrying a floating point value (maybe
current or voltage).
Connecting a 'wreal' to reg doesn't really pose much of a problem if you define the
resolution functions properly, it's similar to connecting it to an analog net (which
is a mostly solved problem).
BTW, I never considered 'wreal' an analog thing, it is really a digital simulation
extension.
> The problem still exists with having "interfaces" connected to "physical" connections through the hierarchy. Perhaps Stefan Boyd's observations are the correct one. The transform has to be handled in the Verilog code somewhere. Unfortunately this is not clear how to do it in the context of configuration switching and netlist generation without either manual manipulation or implicit behavior.
[I'm not sure what you been by 'physical' connections through the hiararchy.]
The reason for making the restriction to 'physical' wire types on implicit and/or untyped
connections is that signal resolution can be handled as in Verilog-AMS by looking solely
at the driver and receiver types across all the domains of simulation involved. Interfaces
can be connected using an appropriate modport.
My concern with interfaces is: how do they work with back-annotation?
Kev.
> -----Original Message-----
> From: Kevin Cameron x3251 [mailto:dkc@galaxy.nsc.com]
> Sent: Monday, September 24, 2001 2:04 PM
> To: david_smith@avanticorp.com; stefen@boyd.com
> Cc: vlog-pp@eda.org
> Subject: RE: Handling of "implicit" declarations
>
>
>
>
> A quick comment: I think implicit declarations should be restricted to
> work only for physical types (i.e. those that end up as single wires
> in Verilog simulation and Silicon) and arrays of those types of matching
> width.
>
> In the same vein, we need to differentiate between a ports of type
> (say) integer which are 32-individual wires of 1 bit and a single
> wire with a set of values.
>
> There are mechanisms described in Verilog-AMS proposals for handling
> mixed analog & digital signal resolution on a single wire that can be
> extended to handle arbitrary data types, but it is extremely difficult
> to do resolution when the physical representation of the data type is
> unknown.
>
> Regards,
> Kev.
>
>
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