Subject: RE: Handling of "implicit" declarations
From: David Smith (david_smith@avanticorp.com)
Date: Mon Sep 24 2001 - 17:27:54 PDT
What is a wire? The Verilog-AMS mechanism for wreal should not be required when using Verilog++ since reals are well behaved.
What is a physical type? Not defined in the language.
Maybe the concept of wire is good but what about busses (they are physical too from the point of view of place and route)? They do not behave well when a wreal is connected to a reg (Verilog rules say to take the least significant bit only on implicit connections).
The problem still exists with having "interfaces" connected to "physical" connections through the hierarchy. Perhaps Stefan Boyd's observations are the correct one. The transform has to be handled in the Verilog code somewhere. Unfortunately this is not clear how to do it in the context of configuration switching and netlist generation without either manual manipulation or implicit behavior.
David
-----Original Message-----
From: Kevin Cameron x3251 [mailto:dkc@galaxy.nsc.com]
Sent: Monday, September 24, 2001 2:04 PM
To: david_smith@avanticorp.com; stefen@boyd.com
Cc: vlog-pp@eda.org
Subject: RE: Handling of "implicit" declarations
A quick comment: I think implicit declarations should be restricted to
work only for physical types (i.e. those that end up as single wires
in Verilog simulation and Silicon) and arrays of those types of matching
width.
In the same vein, we need to differentiate between a ports of type
(say) integer which are 32-individual wires of 1 bit and a single
wire with a set of values.
There are mechanisms described in Verilog-AMS proposals for handling
mixed analog & digital signal resolution on a single wire that can be
extended to handle arbitrary data types, but it is extremely difficult
to do resolution when the physical representation of the data type is
unknown.
Regards,
Kev.
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