Subject: Handling of "implicit" declarations
From: David Smith (david_smith@avanticorp.com)
Date: Thu Sep 20 2001 - 11:33:34 PDT
Greetings,
During our last meeting it was suggested that I put together an example and some thoughts on why implicit declarations are important. Here it is.
There are three different classes of use that I expect that Verilog-PP will be used for.
The first is in system design where the description consists of connecting blocks with logical communication channels. The behavior defined in the blocks describe the interaction and reaction to the information provided on the connection. This can be very abstract. The new addition of "interfaces" provides a wonderful mechanism of defining the interconnect in such a way that the detail of the information is hidden from the connection and can be modified and refined. The support for all variables on ports is also a good addition.
The second class of use is the traditional use of Verilog. In this case the connections provide for the transfer of information that is strictly state based. All of the reg and net connections that can connect to a module are state based. Since there is only one state representation within Verilog this works just fine. The behavior defined in the blocks (modules) are all well defined. An example of data that cannot be transferred is real data. This must first be converted to a bit representation and the it can be passed between blocks. This is not a restriction in system design but is appropriate when the design model is purely logical implementation (RTL).
The third class of use is in mixed-signal design where the description consists of the state connections of Verilog, the abstract connection of real data, and the new concepts of conservative/signal flow connections and behavior required to describe analog behavior.
Now consider a design that has been started at the system level. All of the modules and connections are defined using interfaces and modules. As I decompose (design/implement) a given module I define any interconnections and sub-modules using RTL. If I have to modules at the top level that were interconnected using interfaces but described in terms of RTL then everything is fine. As I implement more blocks I am going to reach the condition where the interconnect information I want to see is not an interface but the net/reg definitions. This requires me to change ALL connections to the interface (even those that are still NOT implemented). This seems awkard.
Consider further the problem where I have implemented most of the design at the RTL level (for the pure digital) and at the mixed-signal level. This will require some of the connections to be net/reg connections, some must be abstract types, and some using "disciplines" (conservative and/or signal flow data types). Keeping track of which type is being propogated is truly a nuisance in any reasonable hierarchy. The problem is now worse when we decide that we wish to choose a different configuration for one of the modules. Take the case in the following diagram. Module A is the top of a design tree. Within Module A there is an instance of module A1, B1, and C1.
Net1 connects port P1 on module A1 to port P1 on module B1
Net2 connects port P2 on module A1 to port P1 on module C1
Net3 connects port P2 on module B1 to port P2 on module C1
Within Module A1 there is an instance of module A2.
NetA_1 connects port P1 on A1 within A1 to port P1 on A2
NetA_2 connects port P2 on A1 within A1 to port P2 on A2
etc...
Module A
Module A1 P1:Net1:NetA_1 P2:Net2:NetA_2
Module A2 P1:NetA_1 P2:NetA_2
Module B1 P1:Net1:NetB_1 P2:Net3:NetB_2
Module B2 P1:NetB_2 P2:NetB_2
Module C1 P1:Net2:NetC_2 P2:Net3:NetC_1
Module C2 P1:NetC_1
Module C3 P1:NetC_2
These nets are not used in any behavioral statements (for simplicity). The version of A2 starts as a System description. Net1 and Net2 must be interfaces. Now, using the Verilog configuration capability (or the Hierarchy Editor in Cadence) change the implementation of modules A2, B2, C2, and C3 to be an RTL implementation. These have net/reg ports. Now all instance of all parents must be changed from interfaces to net/reg ports etc...
The same happens when we go from a system or rtl implementation to a mixed-signal/analog implementation. All connections up the hiearchy have to be redeclared. It the port types are inerited (interface, net, reg, discipline) then the only requirement is that at the type of elaboration any explicit declarations must match. The implicit one change as required. This is enough of a nuisance with a small example. Think about a large design, it will be expensive without either having tools that do this for you automatically or defining it in the language. VHDL/VHDL-AMS made the choice to force the user to manage this. System-C has the concept of everything being an interface (wire and discipline would be derived from the interface so would not require re-connection). Verilog is doing it sometime but not for all... The example is NOT dependent on mixed-signal. The problem exists with just interfaces and reg/nets and variables.
I hope this makes sense.
David
David W. Smith
Architect
> Avant! Corporation
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