Subject: RE: Handling of "implicit" declarations
From: Kevin Cameron x3251 (dkc@galaxy.nsc.com)
Date: Mon Sep 24 2001 - 14:04:29 PDT
A quick comment: I think implicit declarations should be restricted to
work only for physical types (i.e. those that end up as single wires
in Verilog simulation and Silicon) and arrays of those types of matching
width.
In the same vein, we need to differentiate between a ports of type
(say) integer which are 32-individual wires of 1 bit and a single
wire with a set of values.
There are mechanisms described in Verilog-AMS proposals for handling
mixed analog & digital signal resolution on a single wire that can be
extended to handle arbitrary data types, but it is extremely difficult
to do resolution when the physical representation of the data type is
unknown.
Regards,
Kev.
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