Subject: New Dates and New Plans - IMPORTANT
From: Vassilios.Gerousis@Infineon.Com
Date: Tue Sep 18 2001 - 11:44:08 PDT
Hello Everyone,
First of all, I would like to ensure that none of you have been affected in terms of family or friends in the attack to our homeland.
Like anything we are currently affected with cancellation of the conference. Now it has been arranged for November 13 in San Jose. Based on this I would like to propose the following:
1- Hold our regular conference call, with the same number and the same time.
2- We will discuss how to proceed to achieve our next milestone.
3- Please put this into you note book schedule, I would like to schedule a FULL day face to face meeting on November 12. If you have issues, please let me know.
Now for September 24 meeting, please use the same call number (1 405 244 5555 access code 3715) at the same time (9:00 AM PT). Few days earlier, Stu will publish our first Accellera draft. These are the goals that we need to achieve:
1- Vote on the acceptance of the ESS donations. By this vote, ESS becomes the ownership of Accellera. This may encourage few of you to hopefully build prototypes tools to examine areas of difficulties or ease.
2- Develop Document Content for the Verilog++ standard.
3- Review List of issues and ask for volunteers to help in developing proposals or counterproposals.
Based on the above, here is my proposed agenda for the 24:
1- Quick feedback on Accellera draft.
2- Review of action items.
3- Review of issue list (Kelf and Stu should combine their list and produce one).
4- Determine other requirement:
a- Assertion Language construct, semantic and BNF --- Responsibility John Emmit.
b- Additional 2001 enhancements that should be included -- Responsibility Cliff and Stu.
c- Interface section re-write. ??
d- others
5- Determine our next actions (biweekly calls?, team formations, etc.) Until our face to face meeting (planned for November 12).
6- Our major milestones:
a- Accellera draft and Vote on ESS (September 24).
b- HDLCON -- Our first Public draft standard.
c- May 2002 -- Vote to release to Accellera board for standardization.
d- June 2002 -- Accellera standard approval and release of Verilog++.
If there is any change or modification, concern, please let me know.
Best Regards
Vassilios
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Dr. Vassilios Gerousis Infineon Technologies
DAT CAD, MchB
Telephone: +49-89-234-21342 BalanSt. 73
Fax: +49-89-234-23650 D-81541 Munich
email: Vassilios.Gerousis@infineon.com Germany
Site Map: http://www.stadtplandienst.de/query;ORT=m;PLZ=81541;STR=Balanstr%2E;HNR=73
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