Subject: Re: Begin-End / { } / < > ?
From: Kevin Cameron x3251 (dkc@galaxy.nsc.com)
Date: Mon Mar 04 2002 - 09:59:47 PST
> From owner-vlog-pp@eda.org Sat Mar 2 10:16:45 2002
>
> Hi, All -
>
> We have all complained for years that Verilog requires begin-end while the
> C-Language uses { }.
>
> I know we can't use { } because they are part of concatenation and replication.
>
> Could < > be parsed unambiguously in place of begin-end? Since less-than,
> greater-than and shift operators must each appear between two operands, I
> was wondering if compiler writers could easily distinguish < > used as
> begin-end. Just wondering.
C also lets you do:
[<lhs> =] (<expression>,<expression>,<expression>);
- where the result of the block is the last expression on the list. You
could extend Verilog to do the same with ';' instead of ',' and then you
would be able to do what you want with "( )" by not bothering with the
<lhs> assignment.
The C syntax is handy for creating complex (RHS) macros.
Kev.
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